Reconfigurable scan architecture for test power and data volume reduction

Abstract

With exponential development in the semiconductor technology in recent years, the magnitudes of test power consumption and test data volumes have increased significantly. This has resulted in over-testing because of IR drops. This paper proposes a reconfigurable scan architecture to overcome these challenges. The proposed architecture increases the flexibility of the scan partitioning technique to maximize the reduction in the switching activity, and it uses the scan segment skip technique to reduce the data volume. The results show that our method is able to achieve significant reductions in the total test power and data volumes compared with previous methods.