The goal of this study was to investigate the manufacturing error correction model of the wavelet transform processor (WTP) using surface acoustic wave (SAW) devices. The motive of this work was prompted by the output accuracy of the WTP using SAW devices varying with the manufacturing accuracy of each finger of the devices. Thus, in this paper, we presented the functional relationship between the size of the fingers on the layout and their actual measurement values, which are usually equal to their theoretical values we expected. These functional relationships, which also regarded as manufacturing error correction model, can be utilized to eliminate the size shift of each finger generated in the process of device fabrication. The theoretical and experimental results confirmed that the manufacturing error correction model can implement the design of the WTP using SAW devices with high output accuracy.
A novel technique for an optimized deadbeat controller, having higher convergence rate for certain disturbances and capability to maintain the system stability, rapid response and extinction of errors, is presented in this paper. This control law is stimulated with integral control for tracking the reference signals. Moreover, the deadbeat controller is proposed with a state estimator and a disturbance observer for estimating the next sampling interval and to maintain the robustness along with rapid dynamic as well as static response in case of load uncertainty or unpredicted disturbance. The proposed technique is found relatively more effective than the conventional controller and previously designed deadbeat controllers due to its properly designed parameters, as discussed through simulation and by loop experiments in real time hardware assessments.
Redundancy repairs are commonly used to support fault tolerance in DRAM systems and recently, the processor performance has been greatly improved, so DRAM access latency has become an important issue. However, existing redundancy repairs using shift logic have difficulty in further reducing the latency due to their design limitations. In this paper, we propose a novel, decoupled bit shifting technique that uses data encoding and decoding to resolve this limitation. Our technique decouples the conventional shifting logic into two units, a bit selection vector generator (BSVG) and a data manipulation unit (DMU), to reduce the latency overhead of the shifting logic. Our technique can apply the BSVG in parallel with other logic consuming long latency operations, thereby reducing the total latency compared to conventional shifting logic. We implement both serial and parallel approaches to demonstrate that the parallel approach performs significantly better than the serial one in terms of delay, area, and dynamic power consumption. The experimental results show that our bit shifting technique is applicable for redundancy repair technique in state-of-the-art DRAM architectures.
With exponential development in the semiconductor technology in recent years, the magnitudes of test power consumption and test data volumes have increased significantly. This has resulted in over-testing because of IR drops. This paper proposes a reconfigurable scan architecture to overcome these challenges. The proposed architecture increases the flexibility of the scan partitioning technique to maximize the reduction in the switching activity, and it uses the scan segment skip technique to reduce the data volume. The results show that our method is able to achieve significant reductions in the total test power and data volumes compared with previous methods.
To improve the performance of magnetic resonant coupling wireless power transfer (MRC-WPT), a novel conical-helix resonator is designed and optimized for efficient power transfer. Simulation is conducted to investigate characteristics of the proposed resonator and compare with the traditional helix-helix coils. It has been observed that the performance of the MRC-WPT system with conical-helix resonator is superior to that with the helix-helix resonator. Experimental prototype is set up for validation. The results indicate that the voltage transferred to the receiving coil is largely improved for the MRC-WPT system with the proposed resonator when distance between transmitter and receiver varies.
This paper presents a 6-bit 38 GHz vector-summing phase shifter developed for 5G phased array communications. A linear gain adjustment VGA with modified gain control method is presented and is used in phase shifter for vectors weighting. Combined with a degenerated-Q quadrature all-pass filter (QAF) for accurate I/Q generation, high phase resolution is achieved with easy control and compact size. Fabricated in 0.13 um SiGe BiCMOS process, the phase shifter has a measured average insertion loss of 5.7 dB at 38 GHz center frequency, with −3 dB bandwidth of 12 GHz. The RMS phase and gain errors are less than 1.7° and 1.5 dB respectively across 20–45 GHz frequency range over 64 phase states. The chip has a compact core size of 373 um × 311 um and it consumes 11.2 mA from 3 V supply.
An ultra-wideband power amplifier (PA) design employing Real Frequency Technique (RFT) with Gallium Nitride high-electron-mobility-transistor (GaN HEMT) technology is presented. The practical implementation was done with combination of distributed and lumped elements (mixed lumped elements combination) for the need of industrial requirements for the small form factor and low cost. This is an attractive approach for Software Defined Radio (SDR) products to meet wide bandwidth range of 80–2200 MHz. The measured results of the prototype reported good performance over the bandwidth of the interest (i.e. power of 34 dBm to 43 dBm, efficiency about 39% to 69% and gain in the range of 11 dB to 18 dB), and reasonable agreement with the simulated data. According to author’s knowledge, these results are significant for single-ended GaN HEMT device for the wideband operation starting from low frequency 80–2200 MHz.
A fast transient-response digital low-dropout regulator (D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm2. The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. Moreover, the voltage spikes are less than 190 mV.
A novel power-efficient IC test scheme is proposed, containing parallel test application (PTA) architecture and its procedure. PTA parallelizes the stimuli assignments and the vectors can be observed immediately once applied, which assures the shift safety timely and hence only logic test is required. The procedure contains two phases for each pattern. In shift phase, each clock chain is activated in turn and the vectors are assigned in parallel. In capture phase, all chains are captured simultaneously. Experimental results demonstrate that, compared with the traditional serial scan scheme, the proposal reduces average power by 88.48% and peak power by 53.36%.
The RESET current of T-shaped phase change memory (PCM) cells based on Ge2Sb2Te5 (GST) with 35 nm heating electrodes has been studied to understand the influences of RESET current due to the active region via Transmission Electron Microscope (TEM) and testing. The results have been presented and analyzed. Based on the TEM images, it is found that the grains inside and outside the active region have different structures for the operated cells. And the RESET current can be effectively reduced by obtaining larger active region with the grains of Face Centered Cubic (FCC), confirmed by the testing results.
In this paper, we propose low-loss and broadband terahertz (THz) waveguide-to-coupled microstrip transitions using dipole antenna with directors. The simulation and measurement show that insertion/return loss and bandwidth of the waveguide transition can be improved by adding two directors to the basic dipole antenna. The fabricated transition with two directors on a 50 µm-thick quartz substrate exhibits a back-to-back insertion loss of 1.5 dB and return loss better than 15.0 dB across full H-band (220–325 GHz). This belongs to the excellent performance compared with the reported H-band waveguide transitions using dipole antenna.
A novel dual-band antenna by using CRLH-TL structure is proposed for the wireless local area network (WLAN) application. The dual-band behavior is achieved by loading shorted meander lines and interdigital capacitor to form unit-cell CRLH-TL loaded antenna. The bandwidth enhancement of proposed antenna can be achieved by merging the two extended-bandwidth resonances. The dual-band version exhibits two distinct resonances at 2.4 GHz and 5.5 GHz, with measured −10 dB bandwidths of 500 MHz and 2.1 GHz. The lowest resonance at 2.4 GHz corresponds to a 47% reduction in the resonant frequency compared to a reference unloaded monopole. The size of proposed antenna is 30 × 20 × 1.6 mm3. The measured gain reaches −1.6 dBi at 2.4 Hz and 2.6 dBi at 5.5 GHz, respectively. The measurement and simulation results show good agreement.
Among multilevel inverter topologies, asymmetric Cascaded H-Bridge (CHB) inverters have higher output-voltage levels than symmetrical ones. However, asymmetric multilevel inverters need pre-stage isolated and floating DC power sources, which make the system complicated and bulky. This paper is focused on solving the problem by using a single-core (magnetically-coupled) multiple-output forward-flyback converter as the pre-stage of trinary 27-level asymmetric Multi-Level Inverters (MLI). The forward and flyback converter is driven by a single switch with a controller employing both a PWM duty control and frequency control for continuous conduction mode (CCM) forward output and discontinuous conduction mode (DCM) flyback output respectively. Each output, then, can be regulated independently even though the single switch is used. The proposed system and control method are validated using a 1-kW hardware prototype for the experimental verification.
Test data compression is an effective methodology for reducing test data volume and testing time. This paper presents a new test data compression approach based on bit reversion, which compresses data more easier by reversing some test data bits without changing the fault coverage. As there are some don’t care bits in test set, when they are filled, many faults will be repeatedly detected with multiple vectors. Correspondingly, a lot of bits in the test set can be modified without affecting the fault coverage. Experimental results show that the proposed method can increase compression ratio of code-based schemes by around 10%.
In this paper, a feasible compensation technique has been proposed to improve the bandwidth angular stability of FSS radome. Stacked structure composed of different mechanical suitable materials has been adopted to construct the bandwidth compensation layer in the proposed technique. Hence, the problem that mechanical suitable materials with lower permittivity are not available in the classic bandwidth compensation technique has been solved. The validity of the proposed technique is verified by designing an FSS radome composed of modified second-order miniaturised FSS (MFSS) and bandwidth compensation layers. Simulation results show that the proposed technique has equal performance in stabilizing the bandwidth of FSS radome under oblique incidence with the classic one.
A novel dual-band miniaturized frequency selective surface adopting fractal elements is proposed. The proposed structure is composed of interconnected four SZ curves of second generation. Such a design is to provide two pass-bands with stable performance, the first band resonates at S-band with a center frequency of 3.02 GHz and the second band is at C-band centered at 7.22 GHz. In addition, the compact structure employing the space filling curve can further reduce the size of the FSS. The dual-band FSS achieves better miniaturization compared with other single layer FSS in previous literature, the dimension of the unit cell is only 0.072λ × 0.072λ, where λ represents the free space wavelength at first resonant frequency. Furthermore, the proposed FSS exhibits great resonance stability for different polarizations and incidence angles. Both the simulation and measurement verify the stable performance of the FSS.
An improved electrostatic discharge (ESD) protection design, using stacked diodes with silicon-controlled rectifier (SCR), is presented to protect the radio-frequency (RF) integrated circuits in nanoscale CMOS process. Using the stacked diodes and SCR together to form diode-triggered-SCR-like paths, the critical ESD current paths are enhanced. The test circuits of the proposed ESD protection and conventional designs are compared in silicon chip. As verified in a 0.18 µm CMOS process, the proposed design exhibits a lower clamping voltage and higher current handling ability during ESD stress conditions, and sufficiently low parasitic capacitance and leakage current during normal circuit operating conditions. Therefore, the proposed design is suitable for ESD protection of RF circuits in low-voltage CMOS process.