A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system

抄録

A fast transient-response digital low-dropout regulator (D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm². The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. Moreover, the voltage spikes are less than 190 mV.