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IEICE Electronics Express
Vol. 14 (2017) No. 15 pp. 20170591

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http://doi.org/10.1587/elex.14.20170591

LETTER

Recently, with the increasing popularity of data-centric applications, the demand for greater data storage capacities is also growing rapidly. Due to the increased memory footprints, memory system simulators are confronted with serious limitations in exploring memory system behaviors and performances, as the simulation takes enormous time compared to execution in real systems. Furthermore, since emerging memory technologies such as PCM and STT-RAM are designed to execute additional algorithms for enhancing wear-leveling, reducing bit flips, etc., the limitations become worse. To resolve these problems, we propose P-DRAMSim2 that accelerates the most popularly used DRAMSim2, a state-of-the-art memory simulator, by exploiting thread-level parallelism. From our experiment, we obtained up to 15.4× and 15.7× of speedups when simulating DRAM and PCM systems, respectively, with 16 command threads compared to serial execution without any loss of accuracy.

Copyright © 2017 by The Institute of Electronics, Information and Communication Engineers

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