A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes

抄録

In this brief, we propose a novel method which realizes conflict-free strategy in memory-based FFT, of which the hardware complexity is simplified, since only a few extra registers are needed and the control logic is identical in all stages. In addition, we present a modified signal flow graph to fit for the proposed conflict-free strategy. The modified signal flow graph derives from the mixed-radix signal flow graph and has constant geometry property. Furthermore, continuous-flow is adopted to increase the throughput. Thus, the proposed FFT processor has better performance compared with the previous memory-based FFT processors. Simulation result shows that for the proposed 8 to 2048-point FFT processor, the maximum frequency is 400 MHz by using a 65-nm CMOS technology, and the area is 0.45 mm² in the same condition.