IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Reduced complexity polynomial multiplier architecture for finite fields GF(2m)
Se-Hyu ChoiKeon-Jik Lee
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Volume 14 (2017) Issue 17 Pages 20160797

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Abstract

This letter presents a low-complexity semi-systolic array implementation for polynomial multiplication over GF(2m). We consider finite field Montgomery modular multiplication (MMM) based on two-level parallel computing approach to reduce the cell delay, latency, and area-time (AT) complexity. Compared to related multipliers, the proposed scheme yields significantly lower AT complexity.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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