J-STAGE Home  >  Publications - Top  > Bibliographic Information

IEICE Electronics Express
Vol. 14 (2017) No. 17 pp. 20160797

Language:

http://doi.org/10.1587/elex.14.20160797

LETTER

This letter presents a low-complexity semi-systolic array implementation for polynomial multiplication over GF(2m). We consider finite field Montgomery modular multiplication (MMM) based on two-level parallel computing approach to reduce the cell delay, latency, and area-time (AT) complexity. Compared to related multipliers, the proposed scheme yields significantly lower AT complexity.

Copyright © 2017 by The Institute of Electronics, Information and Communication Engineers

Article Tools

Share this Article