Analysis and reduction of the voltage noise of multi-layer 3D IC with multi-paired power delivery network

Abstract

Three-dimensional (3D) integrated circuit (IC) technology has been proposed and used to reduce the delay among layers by shortening interconnection with TSVs. However, large power and ground TSV structures generate voltage noise, and cause additional IR-drop in the power delivery network (PDN). In this work, we investigate and analyze the voltage noise in a multi-layer 3D IC stacking with PEEC-based on-chip PDN and frequency-dependent TSV models. Then, we propose a wire-added multi-paired on-chip PDN structure to reduce voltage noise in a 3D IC. Our proposed PDN architecture can achieve approximately a maximum 29% IR-drop reduction compared with the conventional PDN. In addition, we analyze the layer dependency on 3D IC between the conventional and the proposed PDN models.