Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.

The peak electric field shifting far away from the pn⁻ junction and nn⁻ junction under static avalanche in high voltage diode was investigated by the device numerical simulation in this paper. An analysis of the electric field gradient analytical model was used to explain the reason of the peak electric field shifting. The results show that the peak electric field shifting is essentially induced by the avalanche generated carriers under static avalanche and occurs even at a low reverse current density level. In addition, from the borderline of peak electric field shifting, it is deduced that, with the increases of the surface doping concentration of p buffer layer and n⁻ base region doping concentration, the peak electric field shifting occurs at the higher current density.

This paper presents a compact high-gain, high-efficiency, and broadband (higher than one octave) UHF high-power amplifier (HPA) using gallium arsenide (GaAs) and gallium nitride (GaN) technologies, the broadband HPA was fully integrated in a monolithic microwave integrated circuit (MMIC) with input and output matched to 50 Ω, the total size of the HPA is only 10 × 10 mm². It generates a power gain higher than 44 dB, a continuous wave (CW) output power greater than 10 W and a corresponding power added efficiency (PAE) better than 55 percent across the full band from 220∼520 MHz. This design approach for high power GaN in space saving plastic package is enabling system designers to overcome the challenge to reduce the size, weight, and cost of system designs, while meeting the requirements of higher power, efficiency and reliability.

We fabricated a photonic crystal (PC) laser having a circular defect cavity and a line defect output waveguide based on a heterostructure consisting of a slab layer with quantum dots and an AlO_x cladding layer. The photonic crystal laser was excited by a 785 nm laser diode. Samples with different parameters have similar threshold values of about 25 µm Room-temperature continuous-wave lasing operation at 1.3 µm range is confirmed by observing the spectrum of output light from the line defect waveguide. The wavelengths of the lasing modes show the dependence on the radius of circular resonator and the radius of air holes, which indicate that the lasing mode is the whispering-gallery mode. These results show the feasibility of realizing PC lasers using AlO_x cladding layers.

This paper presents a hardware Trojan classification method that performs a static analysis in gate-level netlist. Based on the controllability and observability characteristics extracted in a circuit, the nets are clustered into two groups with the k-means method. Then inter-cluster distance is measured and taken as the major feature for Trojan identification. By combined with three other features in terms of circuit scale statistic number, a complementary representation of Trojan circuits is constructed. Finally, a support vector machine classifier is trained to distinguish the Trojan circuits from genuine circuits. Experimental results on Trust-HUB benchmarks demonstrate that our method can achieve up to 100% true positive rate.

This paper represents a 4.5 V regulated charge pump with extremely small ripple. The pump designed with Voltage Doubler (VD) significantly reduces the output ripple voltage. In addition, this circuit utilizes a controllable pumping current (CPC) technology, which achieves automatically adjusting output current by feedback mechanism and resizing transfer transistors. The proposed charge pump has been demonstrated in 0.32 µm 3D NAND periphery technology under 3 V power supply. Simulation results show that the output ripple voltage is 1.2 mV at 5 mA load current with 0.1 µF load capacitance. The maximum current drivability and power efficiency is 8 mA and 81% respectively.

A broadband low-noise amplifier (LNA) MMIC with a novel on-chip switchable gate biasing circuit is proposed. The biasing circuit is able to switch on/off the low noise amplifier and compensate the variation of threshold voltage (V_th) and temperature, hence improving the robustness of the amplifier over a wide operating frequency range. The switching frequency is up to 1 MHz, and the fluctuations of on-state quiescent current and power gain of the amplifier are within ±7.9% and ±0.8% when the threshold voltage varies from −0.15 V to 0.15 V. The power gain variation is stabilized within ±1.25 dB by the biasing network, while the temperature changes from −55°C to 125°C. Realized in 0.15 µm E-mode pHEMT technology with size of 2.0 mm × 1.3 mm, the LNA provides a typical gain of 24 dB while maintaining input and output return loss better than 10 dB and the noise figure (NF) of the LNA smaller than 1.6 dB from 4 GHz to 20 GHz.

Homodyne detection of terahertz (THz) waves by a zero-biased Fermi-level managed barrier (FMB) diode was investigated for the first time to reveal its fundamental characteristics in the mixing detection. The lowest noise equivalent power of was obtained at 300 GHz with a very low local oscillator power of 5 × 10⁻⁷ W.

A novel, frequency selective surface (FSS) based, data encoding structure amenable to be used as a chipless RFID tag is proposed. The data encoding structure is made up of finite repetitions of a unit cell fabricated on commercially available grounded FR4 substrate having physical dimensions of 15 × 15 mm². The unit cell is composed of numerous T-shaped resonant elements arranged as two atypical sets of concentric nested loops. Alteration in geometry of the encoding circuit, attained by inclusion or omission of nested resonators, corresponds to a particular data sequence. Each encoded data sequence is manifested in the frequency domain as a distinct spectral signature. The proposed 10-bit tag is both compact and robust, and remains interrogable in response to illuminating electromagnetic waves at various angles of incidence.

In this paper, we propose an optimized bitonic sorting architecture and a hybrid sorting architecture for addressing the sorting problem of successive cancellation list decoders for polar codes. Since half of the 2L metrics are already sorted, lots of redundant sorting operations can be deleted. According to this property and the characteristics of the sorting network, we put forward several optimization strategies to reduce the compare-and-exchange units and the pipeline depths. For the list size L ≤ 32, the synthesis results show that the area of proposed hybrid sorter is at least 22% smaller than existing sorters, and the latency is at least 25% smaller.

A 27-bit circular shaped, highly-dense, fully printable chipless radio frequency identification (RFID) tag is presented in this letter. High data capacity is provided in a compact size. The total dimension of the tag is 22 × 22 mm². For exciting the tag, the linearly polarized incident plane wave is used. The circular shaped tag structure is analyzed for three different substrates, i.e., Rogers RT/duroid^®/5870, Taconic TLX-0 and DuPont™ Kapton^® HN. The spectral range for Rogers RT/duroid^®/5870 is 3.3–13.5 GHz, 3.4–13.6 GHz for Taconic TLX-0 and 3.7–15.1 GHz for DuPont™ Kapton^® HN substrate. Flexibility is achieved by using Kapton^® HN substrate. The presented tag is low-cost and flexible; hence it can be easily deployed on wide range of objects.

It has always been a challenging task to implement a turbo decoder because it’s typically the most compute-intensive and time-consuming part in a wireless communication system. This becomes especially obvious when realizing a turbo decoder through CPUs or GPUs. In this paper, we present a heterogeneous and highly reconfigurable parallel turbo decoder for LTE by employing a multi-core processor platform. A modified sliding-window algorithm is proposed to fully exploit the parallelism of turbo decoder, and a SIMD hardware module is designed for the multi-core processor to accelerate the decoding process. Synthesized result in a 65-nm CMOS process shows that the whole system can run at a maximum clock frequency of 830 MHz, and a decoding throughput of 135 Mbps is achieved for a codeword block length of 6144 at 6 iterations. In addition, the speed-up rate compared to an unaccelerated implementation through the same multi-core platform is in the order of 800%.

A compact low-power current-mode LNA-Mixer with current-reuse architecture used for RF receiving applications is presented. The current-mode mixer reuses the current of the LNA directly to get further minimization on power consumption, complexity and area, making the LNA and the mixer acting as a single circuit. The NF of the LNA is improved by using a capacitive cross-couple structure cooperating with noise suppression inductors. And the single-ended voltage signal is converted to differential current signal so as to improve the common-mode noise rejection ratio. Different from voltage-mode passive mixer, the higher gain compensation and low noise are obtained by switching current mirror method combined with source degradation noise suppression technology. The proposed LNA-Mixer implemented in 0.18 µm CMOS process can obtain a NF of 3.1 dB, a IP_1-dB of −31.6 dBm, a small core size of 0.39 mm² and a power consumption of 8 mW.

This paper presents dynamic standby control (DSC) with voltage keeper for further standby power reduction. As compared to the reported DSC, the new modified DSC can be kept deeply cut-off with negative overdrive voltage as well. Besides, a bootstrapped voltage keeper directly recharges the boosted node of power gate, which prevents leakage current during the recharging period. However, total standby power includes power overhead from DSC. Tuning the recharging rate of the proposed DSC appropriately achieves energy-efficient standby power. As a result, our proposal shows that minimized standby current can be found by an appropriate recharging rate even in different PVT conditions. The design is implemented in 180 nm CMOS process. Measured results show that standby power is suppressed at 0.8 V. Minimum standby power of only 16 nw is achieved where the recharging rate is 10 kHz.

This paper intends to present a novel radiation-hardened SRAM cell by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T. Combined with layout-level optimization design, the 3-D TCAD mixed-mode simulation results show that the novel design has a great single event upset (SEU) immune. Simultaneously, it is found to be tolerant of partial single-event multiple-node upsets (SEMNUs) due to the charge sharing among off-PMOS transistors. In addition, compared with the Quatro-10T, our proposed structure exhibits larger static noise margin (SNM) as well as lower power consumption in 65 nm COMS technology.

Active power filter (APF) is the most popular device in regulating power quality issues. Commonly, a APF controlled current by detected reference current and then tracked the reference current. However, the reference current detection sustain a large amount of computation, in addition, existing error and delay, which effect the dynamic and steady compensation performance of APF. In other hand, a optimal control is based on precise model. However, most literatures modeling in APF singly and rarely considering the impact of grid impedance and load impedance, let alone considering the impact of nonlinear load. Thus this paper established a model consist of LC APF, load and grid impedance, which included disturbance of source voltage and load harmonics current. And then applied linear quadratic regulator (LQR) optimal control in inner current loop design without reference current detection and active damping. Analyzed the effect of grid impedance and load impedance by Bode diagram. At last, compare proposed algorithm with conventional control algorithm. Verified the established model and control algorithm in MATLAB/Simulink and LC APF prototype. The results prove that the established model is correct and the proposed algorithm response fast, compensation harmonics well and is robust in a wide range of parameter variations.

We report a Ka-band monolithic frequency quadrupler with high dynamic range and harmonics efficient rejection based on 0.15 µm GaAs PHEMT process in this letter. The quadrupler is constructed a drive power amplifier, a one-stage active quadrupling part, a high-pass filter, and a three-stage power amplifier of the fourth harmonic. Efficient harmonics rejection is realized by harmonic restrain structure inside the quadrupling part and the filter between the quadrupling part and the output amplifier. According to the measured results, the output power reaches 20 dBm when input power ranges from −5 dBm to 1 dBm at an input frequency of 8.5 GHz. The harmonics rejections are larger than 40 dBc. The overall chip size is 3 × 2.2 mm².

Three-dimensional (3D) integrated circuit (IC) technology has been proposed and used to reduce the delay among layers by shortening interconnection with TSVs. However, large power and ground TSV structures generate voltage noise, and cause additional IR-drop in the power delivery network (PDN). In this work, we investigate and analyze the voltage noise in a multi-layer 3D IC stacking with PEEC-based on-chip PDN and frequency-dependent TSV models. Then, we propose a wire-added multi-paired on-chip PDN structure to reduce voltage noise in a 3D IC. Our proposed PDN architecture can achieve approximately a maximum 29% IR-drop reduction compared with the conventional PDN. In addition, we analyze the layer dependency on 3D IC between the conventional and the proposed PDN models.

In this paper, a scalable large signal GaN HEMT model including nonlinear thermal sub-circuit is described. Only two scalable parameters are needed in the I_ds scalable model by introducing a simple correction factor. The established model can predict the I–V curves at different-in-size AlGaN/GaN HEMTs devices accurately. Small signal S-parameters and large signal load pull tests with on-wafer measurement is used to further validate the proposed model. Finally, the proposed scalable model is used to design a broadband high efficiency continuous class-E power amplifier (PA). Experimental results show that this class E PA is realized from 2.5–3.5 GHz with drain efficiency of 60%–70%, over 8.2 dB gain and over 35.2 dBm output by using a GaN HEMT with 1.25 mm total gate width. The results show that the proposed model is useful for high efficiency amplifier design.

A dynamic log-likelihood ratio (DLLR) scheme based on expectation-maximization (EM) algorithm for the decoding of low-density parity-check (LDPC) codes in NAND flash memory is proposed. When LDPC soft decoding fails, the DLLR scheme employs the EM algorithm to estimate the parameters of the threshold voltage distribution of NAND flash memory, and then recalculates the LLR values for decoding. Simulation results show that the proposed scheme can significantly improve the error correcting performance of LDPC soft decoding in NAND flash memory.

This letter presents a compact dual-band branch-line coupler. Explicit design formulas of the three-branch-line coupler (3-BLC) are derived and useful design curves are given. The equivalent dual transmission lines structure is used to decrease the dimension, and also the partial branch lines are folded to further miniaturize the design. The proposed dual-band (2.45 and 5.8 GHz) coupler has a compact size with 57.6% size reduction compared with the conventional circuit. The measured and simulated results are in good agreement with each other.

This letter proposes highly efficient MISTY1 8-rounds pipe-lined architecture for wireless networks. A novel methodology is adopted for implementation of MISTY1 substitution functions by optimizing S9 and S7 LUTs (Look-Up Tables) to minimize the silicon area. Besides, a key module FI function is compliant to double edge-trigger the optimized S9 LUTs. This leads to substantial reduction in the pipeline requirements for the proposed hardware architecture. For path delay reduction, logic modifications are made in FI and FO functions realizing efficient and high-speed MISTY1 implementation. FPGA implementation on Xilinx FPGA, Virtex 7 xc7vx690t yielded a throughput value of 16.3 Gbps covering area of 1265 CLB slices.