IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
A novel bit flipping decoder for systematic LDPC codes
Jinsoo LimDong-Joon Shin
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2017 Volume 14 Issue 2 Pages 20161100

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Abstract

In this letter, a novel bit flipping decoding of systematic LDPC codes is proposed. Unsuccessfully decoded codeword is efficiently re-decoded by the candidate information bit flipping (CIBF) decoder using cyclic redundancy check (CRC) information at the end of each iteration. We adopt the CIBF decoder to the LDPC decoding additionally and that makes it possible to reduce the power consumption up to 12.7% because of the reduced average number of iterations and to improve the frame error rate (FER) performance. Based on the hardware cost analysis in the CMOS cell library, the additional hardware cost of the CIBF decoder is negligible compared with the conventional LDPC decoder.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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