Cryptosystems are widely used for achieving data confidentiality and authenticated access control. Recent cryptographic algorithms such as AES or RSA are computationally safe in the sense that it is practically impossible to reveal key information from a pair of plain and cipher texts if a key of sufficient length is used. A malicious attacker aims to reveal a key by exploiting implementation flaws in cryptographic modules. Even if there are no flaws in the software, the attacker will try to extract a secret key stored in the security hardware. The side-channel attacks (SCAs) are low cost and powerful against cryptographic hardware. The attacker exploits side-channel information such as power or electro-magnetic emission traces on the cryptographic circuits. In this paper, we will introduce the principle of SCAs and the countermeasures against SCAs.
Side-channel attacks have emerged as the nondestructive threats of security vulnerability in cryptographic hardware. This paper provides an overview of the protection techniques with counter ways of utilizing side-channel information leakage for combatting side-channel attacks as well as securing the authenticity of devices against counterfeits or even falsification.
An enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration was presented. Four transistors were added in this design to transfer bias voltages or ESD voltages. This circuit was simulated in 0.18 µm silicon-on-insulator (SOI) CMOS process and 28 nm HKMG CMOS technology. Spectre-simulation results showed that the ESD discharge current is increased by 2 times and the discharge current is decreased to nA magnitudes compared to the conventional circuit.
This paper presents a transient Pulse Dually Filterable and online Self-Recoverable (referred to as PDFSR) latch. Based on soft error masking property of C-element and using built-in delayed paths combined with a Schmitt inverter, a single event transient (SET) pulse could be dually filtered. Meanwhile, mutually feeding back mechanism of multiple C-elements was constructed to retain data, which makes the latch self-recoverable from a single event upset (SEU). Simulation results have demonstrated the SET filtering ability and SEU resilience at the cost of only 2.0% area-power-delay-width product increase on average, compared with the similar latches.
A parallel parameterizable stream-based JPEG-LS encoder architecture for scalable throughput is presented. The main contribution is the reconfigurable spatio-temporal parallelism to meet different pixel rates for lossless video compression, achieving the required throughputs with lower processing frequencies, scaled by the degree of spatial parallelism. The proposal allows for optimized performance associated to device resources and processing frequency. Experimental results were verified in Altera Stratix I FPGA device.
We present a photonic-plasmonic mode converter using mode-coupling-based polarization rotation for connecting a silicon wire and hybrid plasmonic waveguides on a metal-inserted silicon platform. By using the polarization rotator based on defect-introduced silicon wire waveguide, the proposed mode converter can convert the photonic TE mode into the hybrid plasmonic TM mode. At the beginning, to identify a cross-sectional structure for polarization conversion, we investigate the hybrid parameters that determine the degree of mode rotation using the two-dimensional vector finite element method. Next, using the three-dimensional vector finite element method, we investigate the conversion characteristics of the whole device including input and output ports. Numerical results show that the extinction ratio of 46 dB and the insertion loss of 0.36 dB are achieved. The tolerance of the defect is also numerically evaluated. Our proposed mode converter can reduce insertion losses compared to conventional mode converters based on a taper-introduced butt joint structure.
A new digital delay-locked loop (DLL) for DDR3/DDR4 SDRAM is presented. The proposed digital DLL employs a new noise-tolerant triple (MSB-interval + binary + sequential) search algorithm for implementing a harmonic-free, fast-locking capability while retaining low jitter, low power performance, and a wide operating frequency range. The proposed DLL with duty-cycle correction is designed using a 38-nm CMOS process and occupies an active area of just 0.02 mm2. The DLL operates over a frequency range of 0.3–2.0 GHz and achieves a peak-to-peak jitter of 7.78 ps and dissipates 3.48 mW from a 1.1 V supply at 1 GHz.
The paper proposed a two dimensional (2D) electrical conductivity model based on the solid state plasma concentration distribution model. The results indicated that the imaginary part of the electrical conductivity is more sensitive to the electromagnetic signal frequency than the real part. And the real part is mainly effected by the internal properties of the solid state plasma. Finally, a smart solid state plasma dipole antenna is designed to test the effect of the imaginary part of the electrical conductivity on the radiation characteristics of the antenna. Plasma dipole antenna has also been compared with metal dipole antenna, the results show that the plasma antenna is entirely possible to replace the metal antenna.
A fast-locking fractional-ratio multiplying DLL (FMDLL) for de-skewed on-chip clock frequency multiplication is presented. A new phase detecting controller (PDC) and a dual-path charge pump (CP) have been adopted to achieve shorter locking time and eliminate lock-in fail problems. The proposed fast-locking FMDLL was implemented in a 65-nm CMOS process and occupies an active area of 0.015 mm2. It operates over a frequency range of 2.0–4.0 GHz with a programmable frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4 GHz while consuming 6.7 mW at 2 GHz from a 1.2 V supply. Compared with the conventional architecture, the locking time has been reduced about 80%.
In order to suppress the common mode (CM) noise in high-speed differential signal traces, a compact CM filter is proposed in the letter, which adopts two C-shaped defected ground structure (DGS) cells and one double-headed arrow-shaped DGS cell. An equivalent circuit model is used to explain the working principle of the CM filter. The filter has a small size of 11 mm by 10 mm. It provides a CM suppression from 3.5 GHz to 12.4 GHz over 15 dB, while the differential signals still keep good signal integrity. The experimental results are in good agreement with the simulated results.
This brief analyzes the performance of regulated cascode (RGC) topology and develops a broadband transimpedance amplifier (TIA) incorporated with a novel dual shunt-feedback configuration. Compared to traditional RGC circuit, the proposed TIA improves the natural frequency and optimizes the damping factor. Furthermore, the common source auxiliary amplifier is replaced by an inverter amplifier to provide extra gain and reduce the equivalent input noise current. Based on 0.18-µm CMOS technology, a TIA with enhanced RGC structure was optimized and implemented, and the fabricated chip was mounted on a Rogers 4003C printed circuit board. The experimental results demonstrate a 5.2 GHz bandwidth and a 60.5 dBΩ transimpedance gain for 0.5 pF photodetector capacitance. The fluctuation of group delay is less than 50 ps, and the measured average equivalent input noise current density is about 14.99 pA/√Hz. The chip consumes 28.4 mW using 1.8 V supply.
In this letter, a novel bit flipping decoding of systematic LDPC codes is proposed. Unsuccessfully decoded codeword is efficiently re-decoded by the candidate information bit flipping (CIBF) decoder using cyclic redundancy check (CRC) information at the end of each iteration. We adopt the CIBF decoder to the LDPC decoding additionally and that makes it possible to reduce the power consumption up to 12.7% because of the reduced average number of iterations and to improve the frame error rate (FER) performance. Based on the hardware cost analysis in the CMOS cell library, the additional hardware cost of the CIBF decoder is negligible compared with the conventional LDPC decoder.
A miniaturized frequency selective surface (FSS) composed of wire grid and tortuous pattern of cross-dipole element has been proposed to realize a first-order band-pass response. Resonant frequency of the proposed FSS can be adjusted by changing tortuous factor of the cross-dipole element. Sharper one-side roll-off characteristic and better resonant frequency angular stability can be obtained by the proposed FSS with a larger tortuous factor. Also, by cascading the proposed FSS of different tortuous factors, a dual-band frequency filter property can be obtained. The proposed FSS is analyzed by equivalent circuit method and full-wave simulations.
An ultra-low power low cost LDO (low-dropout voltage regulator) for UHF RFID tag chip is presented. In order to reduce the cost, a low temperature coefficient voltage reference with only 15 KΩ resistor is proposed, this voltage reference is based on sub-threshold operation and the power consumption is minimized. A pole-zero tracking compensation circuit is used, this scheme generates an internal zero which tracks the pole produced by the load current. The design is based on UMC 0.18 µm 2P5M EEPROM process, and the active area is only 0.0146 mm2. The LDO has a maximum load capacity of 5 mA while outputs a 1.1 V stable voltage. The measured undershoot and overshoot are 55 mV and 60 mV respectively. With the ultra-low power voltage reference circuit, the total quiescent current is only 370 nA under a 1.2 V power supply. The proposed regulator has been used in UHF RFID tag chips successfully.
A new method for formulating the equivalent distributed capacitance of NFC coil antenna is proposed. This method is based on an analytical approach by conformal mapping for quantifying the capacitance per unit length and then applied the capacitance network method for calculating the equivalent distributed capacitance. The results of this method are verified with simulated and measured results of two different types of antenna and the agreement is >91%. It is also tested that the capacitance between non-adjacent turns cannot be ignored in the equivalent distributed capacitance computation. Furthermore, the effects of the coil width and gap between the two adjacent coils are predicted in calculating the equivalent distributed capacitance for a specific coil antenna. The proposed method will be useful for designing NFC coil antennas with a better accuracy of capacitance.
A broadband transimpedance amplifier (TIA) is designed and analyzed based on Regulated Cascode (RGC) configuration with L-matching network and cascode amplifier. A novel single-to-differential amplifier is also designed to simplify the following limiting amplifier (LA) design and increase the immunity of common-mode noise. The TIA is implemented in UMC 0.18 µm standard CMOS process. The measured transimpedance gain is 57 dBΩ with a −3 dB bandwidth of 8.1 GHz. The average equivalent input noise current spectral density is 29 pA/√Hz. The chip consumes 68 mW DC power under 1.8 V and occupies the area of 0.9 mm2.
This paper presents a modularized buck-boost and series LC converter (BBSLCC) circuit for series battery equalizers. The proposed topology has numerous advantages. First, the number of switches in the equalizer is equal to the number of the battery cells needs to be balanced in the string. This is so called one-switch-per-cell, which is a great advantage over the traditional buck-boost converter, since it requires almost two-switch-per-cell to balance. Second, unlike many other existing one-switch-per-cell equalizers, the proposed circuit has the advantage in the modularization design and low voltage stress requirement on the switches. Third, the peak current of the balancing capacitor are suppressed by the synchronous phase-shift controller (SPSC) which can be easily implemented by sensing the zero crossing of the LC resonant current. By using the proposed controller, the speed of the battery equalizing process is also accelerated. In this paper, the proposed topology is first presented, and the operating principle is illustrated. Afterwards, the phase-shift time and the transferred energy of the BBSLCC circuit are calculated to demonstrate the proposed control strategy details. The relationships between the phase-shift time and other circuit parameters such as the inductance and the capacitance are also analyzed. The simulation results and the experimental results are finally demonstrated and verified the theoretical analysis on the performance of the proposed BBSLCC circuit.
The random telegraph signal (RTS) noise causes important reliability issues. Complex RTS noise is frequently observed by more than two traps. Originally, it is supposed that the capture and emission between these two traps proceed independently. 4-level complex RTS noise was observed and the characteristics of two individual traps were investigated by using two different methods, which are dependent or independent on capture and emission process between two traps. Thus, the capture and emission dependence of one trap on the state of the other trap, which is trapped or de-trapped, is made clear in conventional and high-K metal gate MOSFET.
A high-resolution column-parallel folding-integration/cyclic cascaded (FICC) ADC with a pre-charging technique for CMOS image sensors is presented in this paper. To achieve high-resolution data conversion with multiple sampling, a pre-charging technique is applied to the sampling circuits of the FICC ADC to reduce the influence of incomplete discharging of historical previous samples. This technique effectively reduces differential nonlinearity of the ADC. The prototype chip with 1504 columns FICC ADC array has been implemented and fabricated in 110 nm CMOS technology. The measured DNL of column-parallel FICC ADC with 128 times multiple sampling is −1/4.73 LSBs in sampling speed of 13 KS/s and 19-bit resolution.
This paper presents a 3.2-to-4.6 GHz fast-settling all digital fractional-N phase-locked loop (ADPLL) for multimode multiband receivers. Firstly, in this ADPLL, the wideband digitally controlled oscillator (DCO) is designed with a constant frequency step in the Coarse Mode to ensure constant loop bandwidth in the whole frequency range. Secondly, a feed-forward presetting path between frequency command word (FCW) and oscillator tuning word in the Coarse Mode (OTWC) is utilized to accelerate the locking process for large frequency hopping steps. Thirdly, an adaptive locked and unlocked controller (ALUC) is used to allow frequency mode (Coarse/Medium/Fine Mode) to shift automatically. Implemented in a 65 nm CMOS process, the ADPLL on-chip part consumes 16 mW at 1 V voltage supply. The phase noise at 3.982 GHz is −121.8 dBc/Hz@1 MHz. The ADPLL with a final bandwidth of 65 kHz exhibits 55 µs transient settling time for a 1.232 GHz frequency hopping.