IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
An improved phase digitization mechanism for fast-locking low-power all-digital PLLs
Lin-lin XieYang WangShu-shan QiaoYong Hei
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2017 Volume 14 Issue 21 Pages 20170911

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Abstract

An improved phase digitization mechanism is designed to overcome limited lock-in range of low-power all-digital phase-locked loop (ADPLL) with phase prediction and edge snapshot circuit. The proposed mechanism including a dual-mode multiplexer-based time-to-digital converter (TDC) and accessional algorithm is verified in a modelled and simulated ADPLL. Results show that the ADPLL is able to lock in 7.8 µs, i.e., 187 cycles with a 24 MHz reference clock. The ADPLL also has strong recovery capability from sudden disturbance, for instance, it recovers in 8 µs with 0.38% disturbance.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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