In order to eliminate the excess timing margin in integrated circuit due to PVT variations, we propose a low overhead timing error prediction monitor, which has only 14 transistors with negligible power overhead. It can generate a predicted alarm signal when the timing is intense before real errors occur. A bunch of timing monitors are inserted at the end of selected critical paths. When there are timing prediction signals, the system clock will be stretched immediately to avoid real timing errors. Applied on a computation intensive Bitcoin Miner chip under 40 nm CMOS process, the simulation results show that it can operate at a wide voltage range of 0.5–1.1 V. This timing prediction monitor based adaptive frequency scaling system can increase the frequency to 2.1× at near-Vth voltage and 1.21× at super-Vth region compared to the original non-monitored circuit. Thus, it is an effective way to mitigate the effect of PVT variations.
A novel high performance 3×VDD-tolerant electrostatic discharging (ESD) detection circuit using only 1×VDD devices was presented in a 28 nm 1.8 V high-k metal-gate (HKMG) CMOS technology. A sub-path and an enhanced path were adopted in this novel design to increase its trigger current. Two small-sized PMOS transistors were employed to protect this circuit out of gate-oxide reliability issues under normal operating conditions. And there is only one capacitor in our novel circuit to maintain a small layout area. Under the ESD stress events, spectre-simulation results show that the trigger current of our proposed circuit can reach 36.4 mA. And its leakage current is only 2.8 nA at 27°C, 243 nA at 120°C under normal operating conditions.
An improved phase digitization mechanism is designed to overcome limited lock-in range of low-power all-digital phase-locked loop (ADPLL) with phase prediction and edge snapshot circuit. The proposed mechanism including a dual-mode multiplexer-based time-to-digital converter (TDC) and accessional algorithm is verified in a modelled and simulated ADPLL. Results show that the ADPLL is able to lock in 7.8 µs, i.e., 187 cycles with a 24 MHz reference clock. The ADPLL also has strong recovery capability from sudden disturbance, for instance, it recovers in 8 µs with 0.38% disturbance.
Non-volatile memories (NVMs), such as Magnetic RAM and Resistive RAM, have been considered as the potential working or storage memories in the next generation computer architectures, thanks to the various merits, such as non-volatility, low power and high speed etc. However, new technology brings simultaneously new challenges, e.g. reliability issue, before practical applications. Compared with conventional memories, the errors in NVMs are generally asymmetric, resulting in different failure rates for 0-1 and 1-0 bit flipping. Error correcting codes (ECCs) are common solutions for protecting memories from errors. The most widely used ECCs are the single error correction and double error detection (SEC-DED) codes. Unfortunately, they are primarily designed for correcting symmetric errors and their error correction capabilities are limited to only one bit. Regarding the failure characteristics (e.g., multi-bit and asymmetric) of NVMs, conventional SEC-DED codes are not efficiently applicable. This paper proposes an extended coset decoding scheme for NVMs. Our simulation results with a Hamming code (with Hamming distance of only three) as an example show the effectiveness of the proposed decoding scheme. The proposed decoding scheme can also be extended to other linear block codes and is rather suitable for scenarios with multi-bit asymmetric error features.
In this letter, a miniaturized, flexible and high data dense dual-polarized chipless radio frequency identification (RFID) tag is presented. The tag is designed within a minuscule footprint of 29 × 29 mm2 and has the ability to encode 38-bit data. The tag is analyzed for flexible substrates including Kapton® HN DuPont™ and HP photopaper. The humidity sensing phenomenon is demonstrated by mapping the tag design, using silver nano-particle based conductive ink on HP photopaper substrate. It is observed that with the increasing moisture, the humidity sensing behavior is exhibited in RF range of 4.1–17.76 GHz. The low-cost, bendable and directly printable humidity sensor tag can be deployed in a number of intelligent tracking applications.
An accurate two-step offset calibration technique based on body voltage control for PMOS and NMOS devices is presented for dynamic latch type comparator. An efficient implementation of calibration logic is also introduced. Design issues and the function of the proposed scheme are discussed and simulated in 90 nm CMOS.
It is well known that Q factor can be calculated from complex resonant frequency of a non-excitation problem. However, two definitions are used to obtain Q factor from complex resonant frequency. One definition uses the real part of the complex frequency while the other uses an absolute value from the numerator of the Q factor. The meaning and difference of the two definitions is investigated using an RLC series circuit, and the findings are presented in this article.
An area-efficient charge pump (AE-CP) used for embedded flash memory is proposed with the combination of an area-efficient voltage doubler (AE-VD). An optimized strategy for AE-CP with local boost technique is discussed to maximize output capability by using low-voltage MOS capacitors together. The proposed circuits are simulated in a 130 nm CMOS process. Simulation results show the proposed AE-VD decreases the power consumption by 11.4%. And the proposed AE-CP with proposed voltage doubler achieves 29% improvement of the maximum output capability as compared to the conventional CP. A 253 × 8 KB embedded flash memory IP has been fabricated in HHGrace 130 nm 4 poly 4 metal CMOS process. The die size of the proposed IP is 0.65 mm2 and the area size of charge pump has been reduced to 0.0317 mm2 with an optimized α = 0.6 and the area ratio decreases by 10%.
We demonstrate power-based refractive index (RI) sensing using a polymer optical fiber (POF) crushed with a slotted screwdriver. This structure can be easily fabricated by simply pressing the end of a slotted screwdriver against part of the POF. Neither external heat sources, chemicals, nor ultrasonic transducers, which have been conventionally used, are necessary. The transmitted power has a linear RI dependence in the RI range from ∼1.32 to ∼1.43 (coefficient: 173 dB/RIU (RI unit)). The temperature dependence of the transmitted power is experimentally shown to be negligible, which indicates the potential of this structure as a temperature-independent RI sensor.
In this paper, we present a new data structure element for constructing a Huffman tree, and a new algorithm is developed to improve the efficiency of Huffman coding by constructing the Huffman tree synchronously with the generation of codewords. The improved algorithm is adopted in a VLSI architecture for a Huffman encoder. The VLSI implementation is realized using the Verilog hardware description language and simulated by Modelsim. The proposed scheme achieves rapid coding speed with a gate count of 9.962 K using SMIC 0.18 micron standard library cells.
A planar millimeter-wave third-harmonic mixer with low conversion loss is proposed. The mixing circuit consists of a substrate-integrated waveguide (SIW) balun, a pair of diodes, a diplexer and microstrip matching circuit. The mixer is ideal for use as down-converter and up-converter. For a fixed intermediate frequency (IF) of 2 GHz, the mixer has an up-conversion loss of 14.5–15.6 dB and a down-conversion loss of 14–15.6 dB over the radio frequency (RF) band of 38–47 GHz. For a fixed local oscillation (LO) frequency of 13 GHz, the mixer has a conversion loss of 10–15.8 dB over the IF frequency band of DC-6.4 GHz. The proposed mixer offers an effective and low-cost solution for millimeter-wave applications.
Polarimetric measurement can gain more object information when compared to traditional methods. Linear polarization ratio (LPR) of the millimeter-wave thermal emission has been presented recently and proved to be effective in material classification. The LPR classification technique can be used for the metal detection in the soil and concrete ground. The roughness has not been considered in analysing LPR properties and it may affect the classification performance. In this paper, we focus on the influence of surface roughness on LPR. By solving scattering problem, the LPR properties of different roughness parameters are investigated. Theoretical calculations indicate that the LPR value decreases with the increasing of surface roughness. In addition, the applicable scope of LPR classification technique to discriminate rough surfaces is discussed.
A third-order single-bit delta-sigma modulator is presented in this paper. An op-amp dynamic current biasing technique is used to improve the power-efficiency of the modulator. The voltage reference block is integrated with the delta-sigma modulator core to avoid the use of large off-chip bypass capacitors and to minimize pin numbers. It achieves 89.2 dB dynamic range over 10 kHz signal bandwidth with an oversampling ratio of 128. The delta-sigma modulator core and on-chip voltage reference block consume 880 µW and 550 µW, respectively, from a 1.8 V power supply. The prototype chip occupies 1.26 mm2 using a 0.18 µm CMOS technology.