An improved phase digitization mechanism for fast-locking low-power all-digital PLLs

抄録

An improved phase digitization mechanism is designed to overcome limited lock-in range of low-power all-digital phase-locked loop (ADPLL) with phase prediction and edge snapshot circuit. The proposed mechanism including a dual-mode multiplexer-based time-to-digital converter (TDC) and accessional algorithm is verified in a modelled and simulated ADPLL. Results show that the ADPLL is able to lock in 7.8 µs, i.e., 187 cycles with a 24 MHz reference clock. The ADPLL also has strong recovery capability from sudden disturbance, for instance, it recovers in 8 µs with 0.38% disturbance.