A novel high performance 3×VDD-tolerant ESD detection circuit in advanced CMOS process

抄録

A novel high performance 3×VDD-tolerant electrostatic discharging (ESD) detection circuit using only 1×VDD devices was presented in a 28 nm 1.8 V high-k metal-gate (HKMG) CMOS technology. A sub-path and an enhanced path were adopted in this novel design to increase its trigger current. Two small-sized PMOS transistors were employed to protect this circuit out of gate-oxide reliability issues under normal operating conditions. And there is only one capacitor in our novel circuit to maintain a small layout area. Under the ESD stress events, spectre-simulation results show that the trigger current of our proposed circuit can reach 36.4 mA. And its leakage current is only 2.8 nA at 27°C, 243 nA at 120°C under normal operating conditions.