2017 Volume 14 Issue 21 Pages 20170944
An area-efficient charge pump (AE-CP) used for embedded flash memory is proposed with the combination of an area-efficient voltage doubler (AE-VD). An optimized strategy for AE-CP with local boost technique is discussed to maximize output capability by using low-voltage MOS capacitors together. The proposed circuits are simulated in a 130 nm CMOS process. Simulation results show the proposed AE-VD decreases the power consumption by 11.4%. And the proposed AE-CP with proposed voltage doubler achieves 29% improvement of the maximum output capability as compared to the conventional CP. A 253 × 8 KB embedded flash memory IP has been fabricated in HHGrace 130 nm 4 poly 4 metal CMOS process. The die size of the proposed IP is 0.65 mm2 and the area size of charge pump has been reduced to 0.0317 mm2 with an optimized α = 0.6 and the area ratio decreases by 10%.