Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

抄録

A transceiver for a 25.8 Gbps/lane with a re-timer IC has been developed for information and communication equipment. Since a 1-unit interval (UI) is very narrow at 38.8 ps at 25.8 Gbps, power integrity (PI) jitter due to power supply fluctuation cannot be ignored. In this paper, we proposed a decoupling-capacitors (Decaps) placement technique to reduce power distribution network impedance (Zpdn) and a circuit design procedure regarding power supply fluctuation. The re-timer IC adopted from the proposed procedure achieved a bit error rate (BER) lower than 1 × 10⁻¹² on backplane transmission with an insertion loss (IL) of 40 dB.