2017 年 14 巻 3 号 p. 20161159
This paper presents a 40-Gb/s 3-tap forward feedback equalizer (FFE) incorporating broadband active delay cell, multiplier & summer and a delay-locked loop (DLL). The active delay cell employs capacitive degeneration and negative impedance structures to broaden the bandwidth. The source-degenerated linear transconductor based multiplier & summer circuits are used through appropriate setting of the FFE tap coefficients. The delay time of the delay cells are calibrated by a DLL against process, voltage, and temperature (PVT) variations. For improving calibration accuracy, the phase detector adopting two symmetric XOR gates and the charge pump utilizing current splitting and self-detection compensation techniques are designed. The proposed circuit is fabricated in 130 nm BiCMOS process, which achieves a data rate of 40 Gb/s through 20-inch FR-4 PCB trace and the horizontal and vertical eye openings of 0.55 UI and 150 mV.
