IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Optimal horizon size for unbiased finite memory digital phase-locked loop
Sung Hyun YouJung Min PakJeong Hoon Kim
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2017 Volume 14 Issue 3 Pages 20161184

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Abstract

Digital phase locked-loop (DPLL) is a circuit system for frequency synchronization, and unbiased finite memory DPLL (UFMDPLL) is DPLL using a finite impulse response (FIR) filter for phase detection. This letter proposes a novel method for finding the optimal horizon size, which is a key design parameter of UFMDPLL, based on the minimization of the estimation error variance. The effectiveness and efficiency of the proposed method are demonstrated in comparisons using the conventional Monte Carlo simulation method.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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