Optimal Horizon Size for Unbiased Finite Memory Digital Phase-Locked Loop

Abstract

Digital phase locked-loop (DPLL) is a circuit system for frequency synchronization, and unbiased finite memory DPLL (UFMDPLL) is DPLL using a finite impulse response (FIR) filter for phase detection. This letter proposes a novel method for finding the optimal horizon size, which is a key design parameter of UFMDPLL, based on the minimization of the estimation error variance. The effectiveness and efficiency of the proposed method are demonstrated in comparisons using the conventional Monte Carlo simulation method.