IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop
Yang LiHua CaiChen Xiaowen
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JOURNALS FREE ACCESS

2017 Volume 14 Issue 5 Pages 20170027

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Abstract

This paper studies the impact of adjacent transistors on the SEU sensitivity of the DICE flip-flop. We compare the SEU sensitivity of the DICE flip-flop with two different layout topologies. Heavy ion experiment results indicate the separation layout topology can reduce the SEU sensitivity of the DICE flip-flop, both in SEU threshold and SEU cross section. TCAD simulation is used to investigate the mechanisms. Simulation results indicate the higher charge collection capability of adjacent transistors in the separation layout topology is the main reason to reduce the SEU sensitivity.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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