The continuous scaling of feature dimensions and the much more complex IC composition are pushing interconnect reliability to its limit, resulting in many fault tolerant interconnect schemes being proposed. At the system level, real-scenario platform simulation is conducted to choose the optimal combination of each part, and various fault tolerant schemes are also compared. In a real-scenario platform simulation, a more practical error model in addition to white noise is needed. So, this paper suggests integrative simple noise and error probability model using the regression analysis with respect to physical behaviors of crosstalk and electromigration. This model can be used in system level simulation to choose an optimal fault-tolerant scheme. In this paper, the integrated crosstalk glitch, and delay model had over 99% accuracy with referenced model, and can apply to system level simulation. 65 nm, 32 nm, 22 nm technologies were used to extract the interconnect parasitic.

In this article, we present a simple MEMS magnetic sensor based on Lorentz Force principle. In this work, the sensor is designed, fabricated and characterized capacitively using a standard capacitance to voltage MS3110 circuit. The sensor is fabricated based on double thickness PolyMUMP surface micromachining process. In this process, the two Poly layers are combined to increase the thickness of the sensor beams and central shuttle. In response to an input excitation current an out of plane motion due to Lorentz force occurs which is detected by the change in capacitance between the moving and static plate. The experimentally detected resonant frequency of the sensor is 5.1 kHz. The experimental sensitivity achieved by the sensor at atmospheric condition is 5.59 V/T for the input current of 30 mA with a damping ratio of 0.010.

Time-frequency domain reflectometry (TFDR) based on electromagnetic theory is first introduced to measure air gap in cables. By using the relationship between propagation velocity and permittivity in electromagnetic theory, the new relationship between the air gap and the propagation velocity in cables can be obtained. The proposed method adopts a chirp signal as an incident signal and uses a normalized cross-correlation function for deriving propagation velocity. To reduce signal distortion caused by cable attenuation characteristics, a modified overcomplete wavelet transform is applied. The air gap volume, which can be measured by the proposed method, can be used as an indicator of poor contact between the cable and connector. The performance of the proposed method is verified through experiments.

This paper presents a 200 kS/s 12-bit successive approximation ADC with a new ladder-based time-domain comparator. The proposed comparator utilizes differential multi-ladder stages, resulting in improvement of gain and noise performance. The chip is designed and fabricated in a standard 0.18 µm CMOS technology with area of 0.127 mm². With a supply of 0.9 V, the ADC consumes 2.72 µW at the sampling rate of 200 kS/s. The measured SNDR and SFDR are 61.6 dB and 66.1 dB respectively, providing an ENOB of 9.9 bits, and the corresponding FOM of 28 fJ/conv-step.

A K-band four-element beamforming system-on-chip (SOC) is presented. In the SOC, the attenuators and the phase shifters, designed in the reflection topology, are realized by two types of the on-chip synthetic transmission lines. The cascode amplifier, as the first stage in the receiving path, provides a gain of 20 dB to compensate all the losses of the passive components, and use dual feedback loops to minimize the group delay variation. The SOC prototype is fabricated by using 0.13 µm CMOS technology, and characterized through the on-wafer measurements. The measured input and output return loss are less than −9.8 and −14.8 dB in the 50 Ω system. The total receiving gain and the noise figure are 5.9 dB and 7.5 dB, respectively. The prototype can continuously make 360° phase shifting with root-mean-square (RMS) errors less than 1.5° and 0.6 dB. The measured group-delay is 249.8 pico-second (ps) with a variation of ±22.8 ps from 22 to 26 GHz. The input P_1dB and IIP3 are −19.8 dBm and −8.3 dBm at 24 GHz. The channel-to-channel isolation is higher than 31.6 dB in a chip area of 0.00632 λ₀² at 24 GHz.

Since the development of optic-fiber interferometers and design of outstanding speech recognition models, the study on perimeter intrusion detection systems (PIDS) becomes a field of interest. In this paper, an optic-fiber based fence intrusion detection and recognition system that uses Sagnac interferometers and mixture Gaussian hidden Markov models (GMM-HMMs) is proposed. Experiments on real fence intrusions are performed, and comparisons are also carried out between our approach and the SVM based method, which prove our system more robust and accurate.

This paper studies the impact of adjacent transistors on the SEU sensitivity of the DICE flip-flop. We compare the SEU sensitivity of the DICE flip-flop with two different layout topologies. Heavy ion experiment results indicate the separation layout topology can reduce the SEU sensitivity of the DICE flip-flop, both in SEU threshold and SEU cross section. TCAD simulation is used to investigate the mechanisms. Simulation results indicate the higher charge collection capability of adjacent transistors in the separation layout topology is the main reason to reduce the SEU sensitivity.

Communication systems usually adopted different encoding structures of convolutional codes (CCs) and turbo codes (TCs). This Letter proposes a unified encoder embedded trellis router (UEETR) to support various decoding of single-binary/double-binary (SB/DB) CC and TC encoding structures with a small hardware overhead. Furthermore, a low-latency UEETR and a hardware-shared radix-4 UEETR are explored to reduce initial setting time and to support radix-4 SB/DB CC and TC decoding, respectively. In addition, a flexible decoding kernel with a small area cost of proposed UEETR has been implemented by a 90-nm process.

A reference column is employed to improve the read performance of phase change memory (PCM). In this way, a changeable reference current replaces the constant one; both the reference cell and the selected cell have the same bit line (BL) parasitic parameters and read transmission gate parasitic parameters in the read operation. Simulated in a 40 nm CMOS process, read access time of 4-Mb PCM is 30.65 ns with 190.9 ns improvement. Monte Carlo simulations show a 80.5 ns worst read access time compared to the conventional 1.58 µs.

An inverter-based class AB amplifier is proposed to design the 11b pipelined analogue-to-digital converter (ADC) in 28 nm CMOS technology. The structure of the proposed amplifier is more concise compared with conventional amplifiers. The amplifier occupies small area, and its quiescent dissipation is only 1.4 mA. This structure is suitable for design in scaled process. The operation of the amplifier is carefully elaborated. The simulation results show: the ADC can achieve 75.3 dB SFDR and 66.8 dB SNDR, while it occupies an area of 0.4 mm² and consumes a power of 17 mW with 1.05 V supply. These results yield a FOMS of 159.3 dB.

Numerous loads require the installation of load transformers for electrical isolation or voltage matching. When these loads are powered by a single-phase on-line UPS system, a high magnitude of transient inrush current is often observed due to the energizing of the load transformer. In this paper, we propose a novel single-phase on-line UPS system that eliminates the generation of inrush current while powering multiple load transformers. The performance of the proposed single-phase UPS system is endorsed by our experimental results obtained using a small laboratory-sized prototype.

In this letter, a class-C architecture for an oscillator employing film bulk acoustic resonator (FBAR) is presented to improve the phase noise significantly in 1/f³ region. The advantages offers by class-C operation are exploited in order to reduce the noise contributed by the current-source transistor in cross-coupled topology. An adaptive biasing circuit is used in order to ensure the oscillation start-up. The post-layout simulation incorporating all parasitic and representing FBAR by modified Butterworth Van Dyke (MBVD) model illustrates the phase noise improvement by 17 dBc/Hz at 100 kHz offset of a 1.9 GHz carrier compared to the FBAR based cross-coupled topology presented by the authors [1].

In this study, the common gate stage of the conventional inductive degeneration cascode LNA operating in 60 GHz V-band for the upcoming Wi-Fi standard, and 802.11ad standard with data rates up to 7 Gbit/sec was linearized by bilateral CMOS resistor. The proposed method linearizes the LNA by 6 dBm with minimum power consumption. The proposed LNA dissipates only 2.05 mW supplied from 1.8 V voltage source and exhibits a minimum noise figure of 6.8 dB in the operating frequency. The LNA, without the proposed linearization technique, exhibited 7 dB gain. The linearized LNA exhibited 3.5 dB gain.

The ADS2016.01 with TSMC 180 nm CMOS model files were used to perform the simulation.

This paper presents an 8-channel time-interleaved SAR ADC. A novel sampling structure is proposed to improve the input bandwidth which also avoids time-skew calibration. The comparator offset cancellation is achieved by body voltage adjustment using low-power charge pump. Each channel has its own on-chip reference buffer to stable reference voltage and correct gain mismatches. The prototype is fabricated in 1P6M 0.13 µm CMOS technology. At 400 MS/s, the ADC achieves an SNDR of 50.84 dB and 45.7 dB at 19.1 MHz and 451 MHz, respectively. It consumes 200 mW, resulting in FOM of 1.76 pJ/con-step.

By extending frequency-domain (FD) asymptotic solutions, we develop novel time-domain (TD) asymptotic-numerical solutions (TD-ANSs), which are new reference solutions on engineering applications, for a transient scattered electric field from a two-dimensional coated cylinder covered with a thick dielectric medium. The TD-ANSs newly include the multiple reflection effect passing through the coating medium as compared with a conventional TD-ANS. The TD-ANSs are highly accurate and are useful because they can extract and interpret each pulse wave element from a response waveform including the multiple reflection effect even when pulse wave elements overlap mutually. The validity and usefulness of the TD-ANSs are confirmed by comparing with a reference solution.