2017 Volume 14 Issue 5 Pages 20170047
An inverter-based class AB amplifier is proposed to design the 11b pipelined analogue-to-digital converter (ADC) in 28 nm CMOS technology. The structure of the proposed amplifier is more concise compared with conventional amplifiers. The amplifier occupies small area, and its quiescent dissipation is only 1.4 mA. This structure is suitable for design in scaled process. The operation of the amplifier is carefully elaborated. The simulation results show: the ADC can achieve 75.3 dB SFDR and 66.8 dB SNDR, while it occupies an area of 0.4 mm2 and consumes a power of 17 mW with 1.05 V supply. These results yield a FOMS of 159.3 dB.