IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor
Taotao ZhuXiaoyan XiangChen ChenJianyi Meng
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JOURNALS FREE ACCESS

2017 Volume 14 Issue 8 Pages 20170218

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Abstract

This paper presents a self-gated error resilient cluster of sequential cells (SGERC) to sample the critical data in wide-voltage operation for EDAC system. SGERC introduces latch-based clock gating technique to error resilient circuits and proposes a customized clock gate which has the ability of timing error self-correction with only two additional transistors added for the first time. Further, it totally eliminates the timing error detection circuits required by each critical register before and utilizes the data-driven clock gating circuits to generate timing error information. Simulation results show that SGERC design achieves 58.3% energy efficiency improvement compared with the baseline design and 19.4% over the latest EDAC design.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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