Multilevel pre-equalization using an analog FIR filter with multiple binary delay lines for 20-Gb/s 4-PAM multimode fiber transmission

Abstract

We propose a novel multilevel pre-equalizer using an analog FIR filter having multiple binary delay lines composed of CMOS inverters. The proposed pre-equalizer can decrease the required circuit scale of conventional analog FIR filters based on binary delay lines. The required number of multiplier circuits was halved by the proposed design scheme in the case of four-level pulse amplitude modulation (4-PAM). The performance was investigated using numerical simulation of a 20-Gb/s 4-PAM multimode fiber (MMF) transmission system. The proposed pre-equalizer successfully compensated the 4-PAM signals, improving the error vector magnitude (EVM) from 40% to 21%.