A low power consumption inverter-based ΣΔ interface for capacitive accelerometer

抄録

A low power dissipation sigma-delta (ΣΔ) interface for closed-loop capacitive accelerometer is presented. In order to reduce the power consumption, the front-end circuit blocks work on a much lower frequency than the electronic ΣΔ modulator, and a cascode inverter with dynamic bias is used as an operational amplifier in electronic ΣΔ modulator, reducing the power dissipation greatly and enhancing the immunity to PVT variations. The measured results indicate that, the total power dissipation is 2.2 mW from a 3.3 V power supply. The noise floor of the accelerometer is 7.2 µg/Hz^1/2 in a closed-loop operation, and the achieved figure of merit (FOM, 8 pW/Hz) is better than the previously reported works.