IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Boosting performance of SSD with chip-level RAID by deferring garbage collection
Jie LiangYongkun LiHao ChenYinlong Xu
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2018 Volume 15 Issue 11 Pages 20180407

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Abstract

Garbage Collection (GC) degrades SSDs’ performance notably, especially for SSDs deployed with chip-level RAID. To address this issue, we propose a deferring garbage collection (DGC) scheme to improve the I/O performance. DGC first predicts whether GC will be triggered on a chip by monitoring its amount of awaiting write requests and the available free pages, and then redirects some pending writes to other “idle” chips so as to defer the GC on busy chips and mitigate the interference between GC and writes. We implement DGC atop a trace-driven simulator. Compared with traditional GC schemes of SSD deployed with chip-level RAID-5, DGC can reduce the average response time by 5.8%–46.7%, and the 99-th percentile response time by 25.3%–77.6%, under different workloads.

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© 2018 by The Institute of Electronics, Information and Communication Engineers
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