Low-density parity-check (LDPC) codes are widely used in NAND flash memory as an advanced error correction method due to their excellent correcting capability. The major challenge is the error floor problem. Dispersed array LDPC (DA-LDPC) code is highly structured and provides implementation convenience due to its regularity. In this paper, it is shown that the constructed (18289, 16384) DA-LDPC code suffers the error floor at BER of 10−9, which is far from the demand of flash memory error control. Carefully observing the error patterns in the error floor region, we propose a concatenation of BCH code to alleviate this issue. The error floor has been successfully brought down to BER of 10−14 by concatenating a BCH code with correcting capability of 14 bits. Compared to the standalone LDPC decoder, the concatenated decoder only consumes 7% extra hardware and the code rate penalty is less than 1%. Meanwhile, hardware implementation has shown that the throughput can achieve 3.52 Gbps with 6 iterations under a clock frequency of 200 MHz.
A silicon X-ray sensor with trench-structured photodiodes was studied and the influence of Compton scattering was estimated. By irradiating the target pixel with X-rays and measuring the signal from adjacent pixels, X-ray scattering and pixel blur of the proposed sensor was determined. An X-ray sensor with a length of 22.6 mm was designed and fabricated, and its modulation transfer function (MTF) was obtained. A sensor structure to improve the MTF level to that of CdTe was proposed.
A wideband package-level driver amplifier in 65 nm CMOS technology is presented in this paper. The inductor-less design is adopted for the inter-stage connection to achieve wide working bandwidth. Bonding wires for the package are modelled and used as the input/output matching networks to minimize the chip size. High-reliability design is adopted and ESD protection circuit, which is able to work under large output voltage swing, are integrated. The proposed amplifier works from 0.72 to 3.65 GHz with 134% fractional bandwidth. The amplifier has 27 dB power gain. The size of the chip is 0.63 × 0.68 mm2.
This letter presents a mismatch-tolerant read-in integrated circuit (RIIC) with voltage-drop compensation applicable to high-speed and high-temperature infrared scene projectors. A current-programmed unit pixel is designed to compensate for ground-line voltage drops, thus improving the array-wide current uniformity. The proposed mismatch-tolerant design circumvents non-monotonic fluctuations in the output current, irrespective of the matching properties of sampling capacitors and switches. A prototype RIIC with a 32 × 32 unit-pixel array is fabricated in a 0.18-µm CMOS process. The RIIC compensates for voltage drops up to 500 mV with error currents below 1 µA and achieves 10-bit accuracy with output-current non-monotonicity eliminated.
This paper proposes a new systolic array architecture to perform division operations over GF(2m) based on the modified Stein’s algorithm. The systolic structure is extracted by applying a regular approach to the division algorithm. This approach starts by obtaining the dependency graph for the intended algorithm and assigning a time value to each node in the dependency graph using a scheduling function and ends by projecting several nodes of the dependency graph to a processing element to constitute the systolic array. The obtained design structure has the advantage of reducing the number of flip-flops required to store the intermediate variables of the algorithm and hence reduces the total gate counts to a large extent compared to the other related designs. The analytical results show that the proposed design outperforms the related designs in terms of area (at least 32% reduction in area) and speed (at least 60% reduction in the total computation time) and has the lowest AT complexity that ranges from 80% to 94%.
Down scaling of photodetectors is one of the major approaches to enhance their performance in terms of operation speed, dark current and sensitivity to photogenerated carriers. In order to compensate for the drawback of the down scaling, i.e. the reduction of light absorption efficiency and light receiving area, this report introduces the bow-tie surface plasmon nanoantenna for silicon on insulator (SOI) nanowire photodiode and clarifies its spectroscopic response. The bow-tie structure has a light sensitive area in the scale of the wavelength, and resonantly enhances the electric field near the central gap resulting in increased generation of carriers in the silicon nanowire, which is experimentally verified and analyzed by electromagnetic simulation.
Conventional high-frequency non-isolated inverter is generally composed of two stages, the step-up stage and the voltage inversion stage, and independent control strategy must exert on each stage. In order to solve the shortcoming, a topological solution (L3 topology) is proposed in this letter, combining the structure of the boost topology and the improved Watkins-Johnson topology to a single stage, realizing voltage step-up and inversion with only three ground-side power switches and single control signal. Theoretical analysis and experimental results validate the feasibility. The merits include ease of driving, small port current ripple, high efficiency, simple control strategy and so forth.
In this paper, a nonisolated three-level (TL) buck converter is used for high voltage high power solar charging application. In order to search the maximum power point tracking (MPPT) point, keep the capacitor voltage balance and realize the function of constant current (CC) and constant voltage (CV) charging, a multiloop interleaved control (MIC) method is proposed. The proposed TL buck battery charger and the MIC method have the advantage of lower inductor current ripple, lower switch withstanding voltage and lower switching loss compared with the conventional buck charger. The proposed MIC method is digitally implemented by a digital-signal-processor (DSP)-based system. Simulation and experimental results based on a 4000 W prototype circuit are presented to demonstrate the effectiveness of the proposed control method.
This paper presents a novel picowatt CMOS voltage reference for energy harvesting (EH) system applications. The output voltage is 133.6 mV with subthreshold operations of MOSFETs at a supply of 0.5 V. It was simulated in 0.18-µm CMOS technology. The simulation results show voltage variation of 0.594%/V line sensitivity for supply voltage from 0.5 V to 3 V and about 3 ppm/°C of temperature variation from −20°C to 80°C. Its power consumption is only 205.027 pW. The power supply rejection ratio (PSRR) has been kept stably at −41.99 dB up to GHz level.
TIADC (Time-Interleaved ADC) architecture suffers from errors introduced by mismatches among the interleaved channels, which degrade performance of TIADC significantly. In this paper, a behavioral model for TIADC based on Wiener model is proposed to describe the nonlinearities in TIADC system. The time-domain and frequency-domain representations of the model are derived. Besides, the discrete-time equivalent model is proposed by transforming the hybrid TIADC model to a purely discrete time system, which is useful for the analysis and implementation of subsequent calibration method. What’s more, numerous studies have investigated compensation methods for discrete-time Wiener model. The methods in these papers can be modified easily for calibration of TIADC using the model proposed in this paper. The experiment results show the nonlinearities of TIADC in practice are consistent with the model proposed in this paper and simulation results indicates the validity of the proposed discrete-time equivalent model.
This paper investigates the impact of mutual inductance (M) on interconnect signal delay estimation according to resistance (R), inductance (L), and capacitance (C) in nano-scale system on a chip (SoC), suggesting a method to predict and suppress the impact. The proposed methodology first calculates the difference in delay between RLC and RLMC wire models for a set of parameter variations, then builds response surface functions (RSF) using physical parameters including wire width and spacing. The proposed method contributes to the following actions.
1) Describe design rules to avoid mutual inductance effects.
2) Select wires which require RLMC models for delay estimation.
3) Correct the estimated delay when using an RLC model.
As an example, situations to limit the mutual inductance effect is shown as to a 14 nm technology node.
For medical implantable devices, power consumption is the most important design consideration. This is because only medium data rate and medium resolution are required in such applications. In addition, rail-to-rail output swing is desired if power supply voltage is near 1 V. In order to achieve low power consumption with medium data rate and resolution, this paper proposes a low-power resistor-string and current-steering hybrid digital-to-analog converter (R-I DAC) with a full-swing output signal. It adopts a current-direction control which makes the output current of the current-steering block flow bi-directionally through the feedback resistor. The proposed structure can achieve full-swing output. It consumes half of the total current of the conventional single-ended current-steering DAC for the same output swing. A 10-bit full-swing R-I DAC prototype is implemented by 180-nm CMOS technology. The measured effective number of bits (ENOB) is 8.9 bits. The settling time of pulse response is 300 ns which corresponds to 3.3 MHz sampling frequency. Chip area is 0.22 mm2. For 1.25 V single power supply, the output swing is 1.024 V. The power consumption is 0.41 mW for a full-swing sinusoidal input of 40.82 kHz at a 3.125 MS/s sampling clock.
A novel hardware-efficient central pattern generator (CPG) model the dynamics of which is described by an asynchronous cellular automaton is proposed. It is shown that the proposed model can generate multi-phase synchronized periodic signals, which are suitable for controlling a serpentine motion of a snake-like robot. The proposed model is then implemented on a field programmable gate array (FPGA) and is used to control a snake-like robot. It is shown by experimental validation using a prototype machine that the proposed model can realize rhythmic locomotor activity in snakes. Moreover, it is shown that the proposed model consumes much fewer hardware resources (FPGA slices) than a typical conventional CPG model. Also, parameter setting methods to adjust the locomotion of the robot are shown.
This paper presents an ultra-wideband (UWB) low noise amplifier (LNA) with low and flat noise figure (NF) as well as high and flat gain using 0.18 µm CMOS technology. Frequency range for both NF and gain is expanded by using current-reuse and weak shunt resistor feedback. The LNA consumes 8.4 mW under 1.8 V. High performances are achieved with the gain of 15.9 ± 1.1 dB, NF of 3.6 ± 0.4 dB within 2.9–10.8 GHz band. The input 1 dB compression point (P1dB) is −17.1 dBm at 7 GHz. The area of the LNA is 0.63 mm2, with pads included.
Garbage Collection (GC) degrades SSDs’ performance notably, especially for SSDs deployed with chip-level RAID. To address this issue, we propose a deferring garbage collection (DGC) scheme to improve the I/O performance. DGC first predicts whether GC will be triggered on a chip by monitoring its amount of awaiting write requests and the available free pages, and then redirects some pending writes to other “idle” chips so as to defer the GC on busy chips and mitigate the interference between GC and writes. We implement DGC atop a trace-driven simulator. Compared with traditional GC schemes of SSD deployed with chip-level RAID-5, DGC can reduce the average response time by 5.8%–46.7%, and the 99-th percentile response time by 25.3%–77.6%, under different workloads.
New topology optimal design approach for optical waveguide devices using a time domain beam propagation method (TD–BPM) is presented. A sensitivity analysis method for topology optimization using TD–BPM is formulated based on an adjoint variable method (AVM). A density method is used as a way to represent refractive index distribution. As design examples, a loss–reduced bending waveguide and a reflector are designed. It is confirmed that our design approach can surely enhance the performance of optical waveguide devices.
An effective method of improving signal integrity of through-silicon-via (TSV) is proposed by adding a PN junction around conventional TSV. And the equivalent electrical model of the TSV with PN junction is proposed, based on which the S-parameters are obtained by ADS software and compared those of conventional TSV. It is shown that the TSV with PN junction offers more superior signal integrity than conventional TSV. Meanwhile, the S-parameters are validated by employing HFSS, and the results from ADS and HFSS show well agreements. Finally, a feasible fabrication process is given.
Fault sensitivity analysis (FSA), as a new type of fault attacks, has been proved a serious threat to the security of cryptographic circuits. It exploits the fault clock to obtain fault sensitivity so as to recover the secret keys. According to the characteristics of FSA, this letter proposes a countermeasure to thwart FSA. We first design a clock check block (CCB) to detect the fault clock which is necessary for carrying on FSA, and then design an enable signal module to change the output of the cryptographic circuit once there is any clock glitch be detected. The implementation results show the proposed CCB can detect the abnormal clock successfully, and our countermeasure can effectively resist FSA. This letter also investigates the hardware overhead of the proposed countermeasure. Compared with these existing countermeasures, although our countermeasure consumes a little more hardware resources due to the extra 495 gates, it has better versatility.
This paper presents a two-stage low noise amplifier (LNA) for 24 GHz automotive radar applications. Compared with traditional common source (CS) stage, the neutralized topology is used to improve the gain and reverse isolation in the first stage. In the second stage, an enhanced neutralized technique is adopted to improve the gain further. The LNA is fabricated by using standard 180-nm CMOS technology and occupies a chip area of 1.0 × 0.8 mm2. The design realizes a gain of 19.8 dB, a noise figure (NF) of 4.7 dB and an input 1 dB compression point (IP1dB) of −12 dBm.