A study on substrate noise coupling among TSVs in 3D chip stack

Abstract

A map of Si substrate noise from through-silicon vias (TSVs) is presented by measurement of real stacked test vehicle. A 65 nm CMOS test chip is manufactured and integrated by die-to-die bonding. The stacked test chip is packaged with an organic interposer and mounted on an evaluation board. A thinned Si substrate is excited through V_DD and V_SS TSVs of noise source circuitry and the noise waveforms are captured by an on-chip evaluation circuitry with 2D mapped probe point on the substrate. The result shows overlapped noise waveforms that as its placement, due to voltage division with Si substrate resistance. A simple Si substrate model is created and employed for first analysis. An analytical result explains measurement result qualitatively including the noise overlapping and cancelling on the Si substrate.