A low-profile wideband unidirectional dipole antenna is presented for the 5G operation. Parasitic strips are utilized for broadband impedance matching at a relatively small height of 4.9 mm (0.067λ0, where λ0 is the free-space wavelength at the center frequency). The measured results show that an impedance bandwidth of 55.4% is realized, ranged from 2.96 GHz to 5.23 GHz. The proposed antenna is with the merits of stable and symmetric unidirectional radiation patterns, low back-lobes and an average antenna gain of 7 dBi over the operating band, making it very promising for 5G system.
This study presents the extraction and verification of a small-signal model suitable for characterizing THz InP double heterojunction bipolar transistors (DHBTs). The π-type topology is adopted in the intrinsic model. Capacitances Ccx and Cce are used to characterize the capacitive parasitics caused by the routing line connecting the collector terminal, base terminal and emitter terminal, respectively. The inductive parasitics introduced by the routing line are also considered. The initial values of the model parameters are extracted using a direct extraction method. The model and extraction method for the model parameters are verified by adopting an InP DHBT with 1 emitter finger and an emitter size of 0.5 µm × 5 µm. The simulation results correspond with the measured results in the frequency range from 200 MHz to 325 GHz.
Based on the AMC (Artificial Magnetic Conductor) reflector, a low-profile and wideband crossed dipole antenna for circularly polarized (CP) applications is presented in this paper. The antenna consists of a double-sided printed crossed dipole radiator, four parasitic loops and an AMC reflector. The crossed-dipole radiator is fed by a pair of vacant-quarter printed rings, generating circularly polarized radiation. By using the parasitic loops, an additional CP mode is produced, which combines with the original CP resonance to provide wideband CP operation. Also, an AMC reflector is used here to obtain unidirectional radiation pattern and the low-profile property. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The results show good performance of 10-dB impendence bandwidth is approximately 50.0% (1.29–2.15 GHz), and 3-dB axial ratio bandwidth of 27.7% (1.4–1.85 GHz). Moreover, the prototype has a low profile of 0.11λ0 (in terms of the center frequency of passband) and an average gain of approximately 8.9 dBic within passband.
In this letter, a wideband spectrum sensing method is proposed for cognitive radio. Firstly, a serial Multi-Coset Sampling (MCS) structure is designed to avoid the mismatch among sub-Analog-to-Digital Converters (ADC) in traditional parallel MCS. Moreover, a five-step spectrum sensing method is presented based on finite resolution power spectral density estimation and energy detection. Finally, sampling pattern design is proved to be a minimal circular sparse ruler problem with an additional constraint. Simulations show that the serial MCS exhibits outstanding detection performance for signals with SNR higher than −3 dB when the number of samples per coset is greater than 1400.
A map of Si substrate noise from through-silicon vias (TSVs) is presented by measurement of real stacked test vehicle. A 65 nm CMOS test chip is manufactured and integrated by die-to-die bonding. The stacked test chip is packaged with an organic interposer and mounted on an evaluation board. A thinned Si substrate is excited through VDD and VSS TSVs of noise source circuitry and the noise waveforms are captured by an on-chip evaluation circuitry with 2D mapped probe point on the substrate. The result shows overlapped noise waveforms that as its placement, due to voltage division with Si substrate resistance. A simple Si substrate model is created and employed for first analysis. An analytical result explains measurement result qualitatively including the noise overlapping and cancelling on the Si substrate.
In this paper, a 12-bit pipeline Analog-to-Digital (ADC) in 0.13 µm CMOS process with SHA-less structure is presented. Two kinds of high-speed comparators are proposed to reduce settling time of residue amplifier. Meanwhile, the foreground calibration algorithm can correct the mismatch of capacitors and alleviate the effect of finite gain of residue amplifier for better linearity. A single-to-differential reference voltage buffer which can be easily controlled by the reference voltage outside is also designed in this ADC. Measurement results show that the ADC achieves an spurious-free dynamic range (SFDR) of 83.6 dBc, a signal-to-noise ratio (SNR) of 67.16 dB and a signal-to-noise and distortion ratio (SNDR) of 66.9 dB with 9.95 MHz input signal at 120 MS/s. The integral nonlinearity (INL) and differential nonlinearity (DNL) are within ±0.8 LSB and ±0.25 LSB, respectively.
A simple analog multiplier for the estimation of the power yield of a solar panel may be realized with a pulse width modulator working as analog multiplier circuit of the current yield and the duty cycle of the converter used to condition the panel. Though the output of the pulse width modulator multiplication is not exactly proportional to the output power of the solar panel, its maximum follows the maximum of the power curve of the panel. This multiplier allows a complete analog implementation of the maximum power point tracker of the panel keeping, at the same time, the simplicity needed in robust electronic systems. This paper presents the working principle of the maximum power point estimator for three different power conditioners of the solar panel: a step-down, a step-up and a SEPIC.
This paper presents a 700-MS/s 6-bit SAR ADC with a novel on-chip reference voltage buffer in a 40-nm CMOS Low-Leakage (LL) process. The reference voltage buffer is partially active depending on the operation state of the SAR ADC. The large driving current is provided only when the Capacitive Digital-to-Analog Converter (CDAC) is settling. This approach achieves 42% power reduction for the reference voltage buffer, which helps to improve the Figure-of-Merit (FoM) of the total SAR ADC chip. The measurement results show the ADC achieves an SNDR of 35.5 dB at the input frequency of 318.8 MHz. The chip consumes 4.0 mW including the SAR ADC core and the reference voltage buffer, resulting in an FoM of 117.8 fJ/conv.-step.
A 14-bit 2 GS/s current-steering digital-to-analog converter (DAC) for transmitter application has been fabricated in TSMC 65 nm CMOS technology. To obtain high linearity, the DAC is segmented as 5+9, where the 5-MSB bits are implemented in unary architecture and 9-LSB bits are implemented in binary architecture. The current source array utilizes the random switching scheme to suppress the graded error and symmetrical error caused by process or thermal gradient. In addition, the DAC’s dynamic performance is enhanced by adopting a digital pre-distortion algorithm and measurement results validate the proposed technique. The measured spurious free dynamic range (SFDR) before and after enabling pre-distortion scheme improves from 63.8 dBc to 70.0 dBc at 240 MHz output signal. Dual-tone and four-tone measurement results show that the DAC achieves the 3rd order intermodulation (IM3) lower than −64 dBc. The DAC occupies an active area of 0.19 mm2 and consumes a total power of 490 mW from 1.3 V and 2.0 V supplies.
In NAND flash memory, a high threshold voltage during incremental step pulse programming speeds up the write operation but reduces the data retention time, and vice versa. Current NAND flash memory uses a low threshold voltage to satisfy the industry standard, which requires data retention of more than a year, and as a result its write operation latency tends to increase as semiconductor process technology progresses. However, actual server workload analysis indicates that much of the data are short-lived and do not require a long retention time. Writing those short-lived data slowly with a low threshold voltage is inefficient. Fast write with a high threshold voltage should be employed for short-lived data and slow write should be employed only for long-lived data. Therefore, this work proposes a method that predicts the lifetime of data based on write request size and selectively applies fast write to short-lived data. The results of evaluations using representative server workloads on an SSD simulator indicate that the proposed method improves an average performance by up to 41.14% compared with the existing method. Further, the increase in total block erasures due to the wrong prediction is limited to 5.60%.
The effectiveness of the compact well contact ring layout geometry in mitigating the single event transients (SETs) in 65-nm bulk CMOS process is studied by technology computer-aided design (TCAD)+SPICE mixed-mode simulations. The SET pulse width is found to be decreased by >8% with this layout approach in normal ion strikes compared with conventional layout design. By well potential control and pulse quenching, the SET pulse is narrowed by >80% when the ion incident angle exceeds 45°, suggesting even better effectiveness for angled ion strikes. The deep N-well process incurs shorter SET pulses compared with the twin-well process due to the funneling length reduction, promising the best SET mitigation effect if the deep N-well process and the compact well contact ring layout are simultaneously used.
This paper presents the design and implementation of a 180 nm CMOS reconfigurable global navigation satellite system receiver, supporting GPS L1, Galileo E1 and Compass B1 bands. The low-IF receiver incorporates a pseudo-differential low-noise amplifier, a double-balanced passive mixer, a pair of trans-impedance amplifiers, a complex band-pass filter, an analog-to-digital converter and an automatic gain control. A phase-locked loop is integrated to provide 25% duty-cycle quadrature clock signals. The RF front-end achieves a maximum gain of 107.2 dB with a dynamic range of 78 dB, a noise figure of 1.8 dB and an image rejection ratio of 39.1 dB.
Bandwidth interleaving digital-to-analog converter (BI-DAC) is a new method for breaking through the bandwidth restriction of the DAC to generate a wideband signal. However, there are some errors in the BI-DAC system such as the aliasing errors caused by the non-ideal performance of the analog filters. To achieve the aliasing errors cancellation, this paper studied the minimax design of digital finite impulse response (FIR) filters. The design goal was to meet a given desired spurious free dynamic range (SFDR) of the BI-DAC system. The problem of designing the digital FIR filters was formulated as a linear programming (LP) problem which could be used to find the global optimal solution of the coefficients of the digital FIR filters. Additionally, this proposed design method performance analysis consist of the computational complexity was derived. Finally, all the proposed designs are verified by both theoretical analysis and numerical simulations, and satisfactory simulation results were achieved.