Effectiveness of the layout approach in mitigating single event transients in 65-nm bulk CMOS process

Abstract

The effectiveness of the compact well contact ring layout geometry in mitigating the single event transients (SETs) in 65-nm bulk CMOS process is studied by technology computer-aided design (TCAD)+SPICE mixed-mode simulations. The SET pulse width is found to be decreased by >8% with this layout approach in normal ion strikes compared with conventional layout design. By well potential control and pulse quenching, the SET pulse is narrowed by >80% when the ion incident angle exceeds 45°, suggesting even better effectiveness for angled ion strikes. The deep N-well process incurs shorter SET pulses compared with the twin-well process due to the funneling length reduction, promising the best SET mitigation effect if the deep N-well process and the compact well contact ring layout are simultaneously used.