High performance AES-GCM implementation based on efficient AES and FR-KOA multiplier

抄録

This paper proposes a FPGA based efficient implementation of AES-GCM for wireless applications. For AES engine, we apply the DACSE algorithm to achieve a compact S-box. A new pipeline strategy is present to improve the throughput of AES engine without bring in extra resource consumption. For GHASH core, FR-KOA algorithm is present to implement a finite field multiplier (FFM). In addition, a 6-stage pipeline strategy is used to improve the FFM throughput. The proposed FR-KOA FFM can match the high-efficiency AES we designed to achieve the highly efficient AES-GCM. FPGA implementation on Xilinx FPGA, Virtex5 xc5vlx85 yielded a throughput value of 48.8 Gbps covering area of 6482 slices. The efficiency of our implementation is 7.54 Mbps/Slice which is higher than the previous works.