IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543

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High Performance AES-GCM Implementation Based on Efficient AES and FR-KOA Multiplier
Yong ZhangNing WuFang ZhouXiaoqiang ZhangJinbao Zhang
著者情報
キーワード: AES-GCM, Highly efficient, FR-KOA, FPGA
ジャーナル フリー 早期公開

論文ID: 15.20180559

この記事には本公開記事があります。
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This paper proposes a FPGA based efficient implementation of AES-GCM for wireless applications. For AES engine, we apply the DACSE algorithm to achieve a compact S-box. A new pipeline strategy is present to improve the throughput of AES engine without bring in extra resource consumption. For GHASH core, FR-KOA algorithm is present to implement a finite field multiplier (FFM). In addition, a 6-stage pipeline strategy is used to improve the FFM throughput. The proposed FR-KOA FFM can match the high-efficiency AES we designed to achieve the highly efficient AES-GCM. FPGA implementation on Xilinx FPGA, Virtex5 xc5vlx85 yielded a throughput value of 48.8Gbps covering area of 6482 slices. The efficiency of our implementation is 7.54Mbps/Slice which is higher than the previous works.

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© 2018 by The Institute of Electronics, Information and Communication Engineers
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