Variable-length and high-precision FFT processors based on configurable constant factor multipliers and memory reallocations

Abstract

A variable-length, high-precision fixed-point pipeline FFT processor design methodology is proposed in this article. As an example for synthetic aperture radar (SAR) imaging processing, a radix-2⁵ single-path delay feedback (SDF) 32768-point FFT is implemented. By analyzing both the two’s complement and canonic signed digit (CSD) representations of the constant factors, the proposed configurable constant factor multipliers (CCFM) can be configured to generate any constant factors applied in the radix-2⁵ algorithm. The variable length architecture can be built up by a simple permutation and combination of radix-2 butterfly operations and CCFM. With the look-up table (LUT) division technique, the twiddle factor storage requirement is significantly reduced. The high precision fixed-point calculation performance is achieved based on a memory reallocation (MR) technique. When performing the non-maximum size FFT, by reallocating the idle memory resources, the fixed-point calculation precision is improved. Compared with conventional design methodology, the proposed fixed-point FFT achieves an SQNR improvement of at least 18 dB and the circuit area is reduced by at least 10%.