In this paper, a novel neuro-space mapping (Neuro-SM) modeling approach for lager-signal transistors is proposed. A new structure of Neuro-SM model with capacitors and inductors is created to change the DC and AC characteristic of the model respectively. An additional current signal extracted with a novel nonlinear function is adopted to improve the large-signal characteristic of existing device models while remain the S-parameters unchanged. A step-by-step training method is developed for fast training of the proposed Neuro-SM model avoiding variables adjustment repeatedly. In addition, the modeling experiment for measurement data of LDMOS transistor demonstrate that the novel Neuro-SM method can accurately reflect the large-signal characteristics of transistor with simple operation process and enhance the accuracy of the existing model.

This paper proposes an energy-efficient and glitch-free digital phase modulator for outphasing transmitter. The proposed modulator uses a path-shared tapped delay line (TDL) and a dynamical pseudo clock-gating control technique. These approaches lead a 64% lower power consumption compared conventional digital control delay lines (DCDLs). Moreover, the proposed modulator achieves circular rotational phase modulation, resulting a system EVM of −36.93 dB and ACLR of −50.96 dBc without extra shaping circuits or analog filters. The prototype modulator was fabricated in 130 nm CMOS process with an active area of 0.134 mm². Operating under 40 MHz frequency with 1.2 V power supply, the proposed modulator consumes total power of 450 µW. In addition, this chip achieves an 80 ps coarse resolution with 4.7 ps RMS error and a minimum phase resolution of 0.96 ps.

It is known that process parameter variation degrades the performance of nanometer integrated circuits. Process variations reduce the maximum clock frequency operation of the chips. Diverse strategies have been proposed in the literature to overcome this issue, especially optimization algorithms (gate-sizing algorithms). However, convergence related problems have limited their use. In this work, a homotopy approach for the design of nanometer digital circuits tolerant to process variations is proposed. Two optimization strategies are developed in this work, the first based on the homotopy continuation method (HCM) and the second based on a modification of HCM, called in this work reboot homotopy continuation method (RHCM). Three logic paths were implemented to validate the algorithms. The optimization results obtained with the proposed strategies are compared with a Lagrange-Multipliers-based framework. Results obtained from HCM method are equivalent to the obtained with Lagrange Multipliers. On the other side, results obtained from the RHCM method are more accurate than the obtained with HCM and Lagrange Multipliers. Furthermore, the area used to implement the logic paths is lower when RHCM is applied. Moreover, the number of Newton-Rhapson iterations required to find the solutions are lower when RHCM is used; consequently, time computing is also lower.

Aging is an important concern in long term reliability of semiconductor devices. In this regard, Bias Temperature Instability (BTI) is considered the major aging mechanism in nanometer regime, particularly in FinFET devices. Therefore, a well understanding of BTI mechanism in FinFET technology is of high interest. In this paper, a three-dimensional TCAD analysis about the impact of negative BTI (NBTI) FinFET technology is presented. In addition, a new NBTI degradation model is proposed for FinFET devices that can be incorporated in Spice which allow to consider aging of a circuit in a design phase. The three-dimensional TCAD analysis is performed using Synopsys Sentaurus tool. Results from the proposed model agree with Sentaurus degradation results.

Although the page sharing among different address spaces can effectively reduce the memory footprint, the corresponding address mappings still require their own TLB entries. Consequently, redundant address mappings for the shared pages reside in TLBs. Our goal in this study is to increase the TLB density by deduplicating redundant copies of address mappings into a single mapping. In virtualized servers, the case of hosting the same guest operating systems, the same third-party libraries, and the same application is commonly found. Such environments generate the multiple identical address mappings, virtual to physical address, for shared pages among different virtual machines. We exploit this unique characteristic of the virtual memory layout being analogous in the same execution environment, and explore TLB deduplication, called DeTLB, which merges redundant virtual to physical address mappings of different address spaces into a single TLB entry. To demonstrate the performance impact, we develop a QEMU based trace simulator and evaluate the number of TLB misses by running an Apache Spark ALS and a microbenchmark with the Linux KSM module. The results indicate that DeTLB can effectively reduce the number of TLB misses for both data and instructions.

We report on a novel design of a wavelength selective switch (WSS) using silicon photonics technology. It comprises of 1 × 4 interleavers, arrayed-waveguide gratings (AWGs) connected to fold-back waveguides, and 1 × 2 optical Mach-Zehnder interferometer switches. In the proposed WSS, fold-back waveguides enable the AWGs to be used for both demultiplexing and multiplexing. Therefore the WSS has less waveguide crossings than a conventional configuration. Moreover, a 20-channel, 200-GHz spacing, 1 × 2 fold-back type WSS was fabricated on 5 mm × 10 mm SOI chip using CMOS technology.

This paper presents design of 14-T 1-bit full adder power efficient Pass Transistor Logic (PTL) based stable circuit. Due to compact architecture, power consumption is low and response is faster. MC (Monte Carlo) shows that the circuit is more reliable against any statistical variations.

This paper proposes a FPGA based efficient implementation of AES-GCM for wireless applications. For AES engine, we apply the DACSE algorithm to achieve a compact S-box. A new pipeline strategy is present to improve the throughput of AES engine without bring in extra resource consumption. For GHASH core, FR-KOA algorithm is present to implement a finite field multiplier (FFM). In addition, a 6-stage pipeline strategy is used to improve the FFM throughput. The proposed FR-KOA FFM can match the high-efficiency AES we designed to achieve the highly efficient AES-GCM. FPGA implementation on Xilinx FPGA, Virtex5 xc5vlx85 yielded a throughput value of 48.8 Gbps covering area of 6482 slices. The efficiency of our implementation is 7.54 Mbps/Slice which is higher than the previous works.

A variable-length, high-precision fixed-point pipeline FFT processor design methodology is proposed in this article. As an example for synthetic aperture radar (SAR) imaging processing, a radix-2⁵ single-path delay feedback (SDF) 32768-point FFT is implemented. By analyzing both the two’s complement and canonic signed digit (CSD) representations of the constant factors, the proposed configurable constant factor multipliers (CCFM) can be configured to generate any constant factors applied in the radix-2⁵ algorithm. The variable length architecture can be built up by a simple permutation and combination of radix-2 butterfly operations and CCFM. With the look-up table (LUT) division technique, the twiddle factor storage requirement is significantly reduced. The high precision fixed-point calculation performance is achieved based on a memory reallocation (MR) technique. When performing the non-maximum size FFT, by reallocating the idle memory resources, the fixed-point calculation precision is improved. Compared with conventional design methodology, the proposed fixed-point FFT achieves an SQNR improvement of at least 18 dB and the circuit area is reduced by at least 10%.

This article investigates the resonant transmission characteristics of periodic subwavelength slits on real metallic plates at terahertz frequencies. By applying the eigenvalues of the slit to the mode matching technique (MMT), the transmission characteristics of the periodic subwavelength slits can be resolved as function of the gap width, plate thickness, and frequency. The resulting transmittance of the proposed method is then verified by comparing it with a commercial electromagnetic simulation software. This study demonstrates that the proposed MMT is suitable for calculating the transmittance of the periodic metal-insulator-metal slits on the real metal material and provides in-depth intuition for resonance phenomena using the modal approach.