2018 Volume 15 Issue 15 Pages 20180611
A push-pull multi-loop architecture for the digital low drop-out (D-LDO) regulators is presented with small variations of output voltage and 200 mA load capacity. The propose D-LDO adopts voltage peak detector (VPD) to observe the output voltage ripples. Once undershoot or overshoot on output voltage is detected, the push-pull feedback loop is quickly triggered, which minimizes the voltage shoots even if the load current changes abruptly. Meanwhile, the shift register (S/R) feedback loop regulates the output voltage to desired value with high accuracy. Hence the D-LDO recovers steady state with greatly small voltage spikes. The proposed D-LDO is designed and simulated in SMIC 65 nm CMOS process with a 0.42 mm2 active area. The simulated voltage overshoot and undershoot are 27 and 26 mV respectively, with load step of 20 to 200 mA with a 10-ns edge time. The max load current and quiescent current are 200 mA and 400 µA, respectively, and the peak current efficiency is 99.8%.
