2018 Volume 15 Issue 17 Pages 20180640
We present an inductorless circuit technique for a CMOS limiting amplifier (LA), which consists of an input buffer, third-order broadband gain stages, and an output buffer for driving 50-Ω transmission lines. By employing stream-mode active feedback with negative capacitance circuit (NCC), the bandwidth of the proposed circuit can be effectively enhanced while maintaining a flat frequency response within the −3 dB bandwidth. Based on TSMC 0.18-µm CMOS process, the proposed LA circuit is optimized and implemented. The measurement results shown that the −3 dB bandwidth is 7.2 GHz with a voltage gain of 41 dB, and a data rate of 9 Gb/s is successfully achieved. The fluctuation of the group delay is less than ±25 ps, and the maximum output voltage is 1 Vpp. The measured noise figure of the LA circuit is about 10 dB. Due to the absence of spiral inductors, the die only occupies a core size of 0.3 × 0.2 mm2, and consumes 79 mW from a 1.8 V supply voltage.
