IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Efficient bit-parallel systolic architecture for multiplication and squaring over GF(2m)
Kee-Won KimSeung-Hoon Kim
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2018 Volume 15 Issue 2 Pages 20171195

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Abstract

In this letter, we propose a parallel-in parallel-out systolic array for concurrently computing multiplication and squaring over GF(2m). For m ≥ 400, the proposed bit-parallel systolic array can save about 50% time complexity as compared to the corresponding existing structure. The proposed array can be used as a core circuit for various applications. Also our architecture is well suited to VLSI implementation as well.

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© 2018 by The Institute of Electronics, Information and Communication Engineers
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