A novel structure of filtering antenna working at a center frequency of 10 GHz with a fractional bandwidth of 10% is presented in this letter. It consists a third-order Chebyshev filter with resonators coupled by shifted layers and an array of two aperture antenna elements in the end. This new structure without any iris is very suitable for machining layer by layer. Therefore, it would be a solution in some special conditions in which traditional ways of manufacture could not be realized. In the end, the antenna array is fricated by computer numeral control (CNC) milling technology. Conclusion and analysis to the measurement are presented, as well as the methods for improvement.

An ultra-wideband low noise amplifier (LNA) is presented in 65 nm CMOS. In order to obtain ultra-wide bandwidth, a compact inter-stage network utilizing one transformer and a de-Q-ing resistor is presented. The proposed LNA achieves maximum power gain of 18.21 dB over an ultra-wideband of 1–13 GHz, the measured minimum noise figure (NF) of 5.28 dB and an input 1-dB compression point (IP_1dB) of −21.43 dBm. The implemented LNA occupies 0.52 mm² of the active area excluding pads, and it draws 14.92 mW from 1.2 V power supply.

In this paper, we propose a highly accurate solenoid valve driver with high- and low-side current sensing circuits. The proposed solenoid valve driver improves the current accuracy by sensing the current of the solenoid coil alternately in the on- and off-states of the power MOS transistor. In the on-state, the low-side sensing circuit senses the current flowing through the low-side transistor. In the off-state, the high-side sensing circuit senses the current flowing through the high-side transistor. The proposed solenoid valve driver was implemented using a 0.11 µm BCDMOS process. The measurement results show that the proposed solenoid valve driver achieves a high current accuracy of less than ±4% over the entire current range from 0 A to 2.25 A.

In this letter, we present a novel memristor-based restricted Boltzmann machine (RBM) system for training the brain-scale neural network applications. The proposed system delicately integrates the storage component of neuron outputs and the component of multiply-accumulate (MAC) in memory, allowed operating both of them in the same stage cycle and less memory access for the contrastive divergence (CD) training. Experimental results show that the proposed system delivers significantly 2770x speedup and less than 1% accuracy loss against the x86-CPU platform on RBM applications. On average, it achieves 2.3x faster performance and 2.1x better energy efficiency over recent state-of-the-art RBM training systems.

Through 90-nm CMOS technology, a K-band fractional-N frequency synthesizer has been designed. This paper proposes a new analysis to evaluate the noise current of the charge pump in fractional-N frequency synthesizer. It also designs an improved charge pump (CP). In addition, it also presents the multi-modulus divider (MMD) by the retime technique. The measured phase noise achieves −93.5 dBc/Hz and −86.88 dBc/Hz for integer-N and fractional-N modes at 1 MHz offset, respectively. The in-band phase noise performance can be improved about 20 dB by the retime technique. −54.63 dBc and −50.7 dBc reference spurs are respectively revealed by the spectrum for integer-N and fractional-N modes.

It is known that perturbation elements realize sub-resonance and they can be applied to a circular patch array absorber for improving its bandwidth. The considerable polarization conversion, however, occur due to the perturbation elements. In this paper, the polarization conversion is suppressed by applying the rotation symmetry arrangement of the elements. As the result, the polarization conversion level less than −30 dB was measured with maintenance of three times bandwidth of the absorber without perturbation elements.

In this paper, a high-resolution Sigma-Delta (ΣΔ) modulator in a standard 0.5 µm CMOS technology for a MEMS accelerometer is presented. The digital output is attained by the interface circuit based on a low-noise front-end charge-amplifier and a back-end forth-order Sigma-Delta modulator. The low-noise front-end detection circuit is proposed with correlated double sampling (CDS) technique to eliminate the 1/f noise and offset of operational amplifier. The capacitance compensation array is used for rejecting the sensor element mechanical offset. The lead compensator circuit is to ensure the stability of the high-order closed-loop system. The interface is fabricated in a standard 0.5 µm CMOS process and the active circuit area is about 8 mm². The MEMS accelerometer system consumes 25 mW from a single 7 V supply at a sampling frequency of 250 kHz. The ΣΔ modulator can achieve an effective number of bits 20.30 bits and an average noise floor in low-frequency range of 140 dB.

This paper proposes an adaptive cache replacement policy to select a victim block based on the reuse characteristics of stored blocks by utilizing the fine-grain reusability monitor for each cache set. The evaluation result shows that the proposed mechanism can achieve a performance improvement of about 13% on average over conventional 2 MB cache and can deliver performance comparable to four times bigger cache, i.e., an 8 MB last level cache (LLC).

This paper presents a single-layer delay-lines based reflectarray for X-band applications. The proposed design contains an octagonal-shaped patch with T-shape delay-lines. A phase range of 500° is realized by using T-shape delay-lines. A stable phase range is achieved for TE and TM modes at 0°, 15° and 30° incident angles. An equivalent circuit model is used to investigate the resonant property of the proposed reflectarray unit element. A 21 × 21 elements reflectarray is designed, fabricated and measured on an FR-4 substrate. The proposed design provides 1-dB gain bandwidth of 18.5% and 3-dB gain bandwidth of 30%. Measured gain of 26 dBi at 10 GHz with aperture efficiency of 65% is obtained. The proposed reflectarray configuration have side-lobe-levels less than −25 dB.

This paper proposes and demonstrates a plane-wave generator which consists of a compact taper array and expands the aperture of the grating waveguide (GWG) of optical leaky wave antenna, resulting in a high antenna gain. The device size is reduced to half of a conventional slow taper without degrading the aperture efficiency. We confirm the well correspondence of the antenna gain between the full numerical simulation and the estimation using measured parameters for the device fabricated by silicon photonics.

A novel combined twist-bend with compact-size and broad bandwidth is proposed in this letter. It provides an interconnection of two waveguides with 90 degrees oriented cross-sections and a perpendicular alignment of their axes. The basic structure consists of a multi-step central waveguide and two transformer sections, which made the twist-bend with compact size and broad bandwidth. For verification purpose, a prototype has been manufactured and measured. Measurements of a WR28 combined twist-bend exhibit a return loss greater than 24 dB and a insertion loss better than 0.1 dB over the full waveguide bandwidth. Also the good agreement has been found between the simulated and measured results.

In this article we present a study about how to obtain a trade-off between two important metrics for IoT systems-Security vs Power Consumption. More specifically, we have studied how the min-entropy of two True-Random number generators can be adjusted dynamically in order to reduce the power consumption while guaranteeing the integrity of the system. To that end, we make use of some statistical tests that are typically used to measure the quality of the RNGs. Clock-gating and enable-gating are the selected techniques to reduce the power consumption.

A graphene frequency tripler (GFT) is proposed. The graphene is similar to anti-parallel diodes, which has nonlinear characteristic. In order to improve the efficiency of the GFT, the output port of the GFT uses the reflector networks to recover the power of the fundamental and fifth harmonic wave. According to the mechanism, a sample GFT is designed, fabricated, and measured. In its operation frequency of 12 GHz to 30 GHz, the minimum conversion loss of −24.2 dB can be obtained at 18 GHz when the input power is 14 dBm.

In this letter, we propose a parallel-in parallel-out systolic array for concurrently computing multiplication and squaring over GF(2^m). For m ≥ 400, the proposed bit-parallel systolic array can save about 50% time complexity as compared to the corresponding existing structure. The proposed array can be used as a core circuit for various applications. Also our architecture is well suited to VLSI implementation as well.

This paper presents a practical, low-overhead, one-cycle correction better-than-worst-case design method for ultra-low voltage digital circuits. Excessive design margin for PVT variation brought by traditional worst-case design method is eliminated. Proposed method is completely compatible with EDA tools. Considerable design efforts are relaxed compared with other variation-tolerant techniques. We have implemented our proposed technique on a 16 bits × 16 bits pipelined multiplier in SIMC 55 nm CMOS process. The experimental results show that our proposed technique can get about 59% energy efficiency improvements compared with operating in worst-case timing margin.

In this letter, we consider a performance evaluation of an analog correlator, and extract Stokes parameters from cross correlation between horizontal and vertical channels of electric fields for a fully polarimetric radiometer. To this end, we develop an analog correlator using 90° and 180° hybrid couplers and square-law detectors. In order for its performance analysis, we derive a closed form of a mathematical representation for Stokes parameters in terms of amplitude and phase responses of both channels, characteristics of hybrid couplers. As a result, the cross correlation of U and V of Stokes parameters is 0.92 and 0.96, respectively. And the maximum return loss of the proposed analog correlator is less than −23 dB for all directions. In addition, the peak-to-peak amplitude response of the proposed analog correlator is 1.9 dB, and for the phase response as 9°. We compare numerical and measured results of I and U of Stokes parameters, and obtain their average errors as 0.4% and 14.9%.

A compact microstrip triple-band bandpass filter (BPF) using an improved quad-mode stepped impedance resonator (SIR) with shorted stub is introduced in this letter. Distinct mode splitting characteristics of the quad-mode SIR are investigated by adopting even- and odd-mode theory. Two pairs of even-odd modes are utilized to design the former two passbands with the help of loop-loop coupling for splitting two identical modes. Then, a tapped side-coupled feed-lines construct an additional passband avoiding occupying extra size. The bandwidth of each passband can be controlled independently. To validate the approach, a triple-band BPF centered at 1.4/2.7/3.57 GHz has been implemented. Good agreement is obtained between simulated and measured results.

A high-resolution capacitive-sensor interface for sub-1mG MEMS accelerometers is presented herein. A time-domain capacitive-sensor interface based on a relaxation oscillator with noise reduction is proposed to achieve a high resolution. A prototype interface is fabricated using a 0.18-µm CMOS process. The prototype is linked with a sub-1mG MEMS accelerometer, and its performance is investigated experimentally. The results confirm that the proposed interface is able to detect sub-1mG acceleration with a signal-to-noise ratio of 90.3 dB (an acceleration noise-floor of 9.0 µG/√Hz with a bandwidth of 12 Hz).