2018 Volume 15 Issue 3 Pages 20171139
This study presents a silicon-based ultra-wideband (UWB) true-time delay line for timed array antennas. The proposed circuit uses the novel active switches to mitigate performance deterioration from on-off switching. The proportional-to-absolute-temperature (PTAT) biasing circuit and scaling technique are adopted to improve the gain stability against the PVT variation at the different delay settings. The experimental prototype is fabricated in a 0.13 µm SiGe BiCMOS process, and exhibits a maximal relative delay of 35 ps with an average of 5 ps over a frequency range of 14–34 GHz. The chip occupies an area of 0.62 mm2, and the measured average input 1-dB compression point is 13 dBm.