This paper presents a compact equivalent lumped circuit model for on-chip helical transformers. From fundamental model, a simple coupled RL loop is added to account for the skin and proximity effect, and a series RLC branch is added to account for the parasitic coupling effects between inductors. Several helical transformers with various design configurations were fabricated using a standard 0.18 µm 1P6M CMOS process. It’s demonstrated that the proposed model shows good accuracy over two times self-resonance frequency, which is essential for the design of high-speed and radio-frequency circuit.
High-speed optical interconnects require compact, low-power driver electronics for optical modulators. Inverter based CMOS driver circuits show very low power consumption. However, the output swing is typically limited to the supply voltage which is typically insufficient for optical modulators, requiring a cascoded output driver and level shifter. In this work, we present a new DC-coupled thin-oxide level shifter topology in a 28 nm FDSOI CMOS technology enabling data rates up to 50 Gb/s with a power efficiency of 0.064 pJ/bit.
This paper presents an amplifier-douler chain to double the signal frequency from 21 GHz to 42 GHz with about 10 GHz bandwidth of output frequency. For the improvement of conversion gain, the doubler adopts the fully differential Gilbert structure which provides large bandwidth and high conversion gain. Meanwhile, an inductive series LC network is used to form resonant tank with the parasitic capacitance to suppress the second harmonic of input frequency, hence the conversion gain of doubler is improved. Once again, the RLC parallel resonant network is employed as load of doubler and power amplifier, and it can improve bandwidth and conversion gain, too. What’s more, transformer matching networks (TMN) are adopted to optimize the bandwidth and conversion gain of amplifier-douler chain. Finally, the amplifier-douler chain which fabricated by IBM SiGe 0.13 µm BiCMOS technology shows 6.1 dB conversion gain and −4.1 dBm saturation output power with 26.5 mA operating current and 2.8 V supply voltage, and the fundamental and 3rd harmonic rejection at 42 GHz are 17.5 dB and 38.6 dB, respectively.
Frequency-domain optical coherence tomography (FDOCT) has been widely applied in medical image inspection. This paper presents an image formation processor capable of performing all FDOCT imaging operations, including DC noise removal, re-sampling, real-valued fast Fourier transform (RFFT), and display processing. A hardware-efficient RFFT unit and memory-based display processing engine make it possible to generate gray-scale display data at high OCT imaging rates. System-level design verification was performed using an FPGA platform and a mobile phone to evaluate the efficacy of the proposed scheme.
In this paper, an improved SEU hardened SRAM bit-cell, based on the SEU physics mechanism and reasonable circuit-design, is proposed. The proposed SRAM cell can offer differential read operation for robust sensing. By using 90 nm standard digital CMOS technology, the simulation results show that the SRAM cell can provide full immunity for single node upset and multiple-node upset. And its critical charge is 25 times compared with Quatro10T. Besides, by comparing several electrical parameters, the proposed SRAM cell has the highly reliable and low-power capability for severe radiation environment application.
This study presents a silicon-based ultra-wideband (UWB) true-time delay line for timed array antennas. The proposed circuit uses the novel active switches to mitigate performance deterioration from on-off switching. The proportional-to-absolute-temperature (PTAT) biasing circuit and scaling technique are adopted to improve the gain stability against the PVT variation at the different delay settings. The experimental prototype is fabricated in a 0.13 µm SiGe BiCMOS process, and exhibits a maximal relative delay of 35 ps with an average of 5 ps over a frequency range of 14–34 GHz. The chip occupies an area of 0.62 mm2, and the measured average input 1-dB compression point is 13 dBm.
This paper proposes an ultra-wide range transmitter with a latched AC-coupled driver (LACD) and a dummy data transient generator (DDTG). The LACD expands the low-frequency range by preventing the capacitor discharge issue of the high-speed AC-coupled driver and the DDTG enhances the high-frequency range by generating a dummy transient pattern to stabilize the power node fluctuation induced by the dense and sparse pattern dependency in the case of coding-less application. A 24-channel test chip designed with 40-nm CMOS technology achieved an ultra-wide frequency range (0.01–10 Gbps/channel) and ultra-wide bandwidth from 0.01 Gbps (0.01 Gbps × 1 channel) to 240 Gbps (10 Gbs × 24 channels) and a high area efficiency (0.0027 mm2/Gbps/channel). At the data rates of 5 and 10 Gbps, the jitters with DDTG were 50% lower than attained without DDTG.
Magnetic sensors based on the giant magneto-impedance effect (GMI sensors) have a promising application prospect in the field of magnetic anomaly detection for their high resolution. However, they are highly sensitive to its orientation without any magnetic shielding. A method that automatically adjusts the bias magnetic field to make it always work on its initial value is proposed in order to suppress output instability of GMI sensors caused by the orientation. The analog circuit implementing the method is designed according to the principle of feedback control. The experimental results demonstrated the effectiveness of the proposed method.
A capacitance multiplier with high accuracy and reduced power consumption and silicon area, is presented. It offers a scaling factor based on ratios of resistors that can be physically matched to reduce deviations due to fabrication process. Resistor ratios also offer the property to define large scaling factors without increasing power consumption or silicon area. It is based on a modified current-mode multiplication technique that scales voltage magnitude instead of internal devices of the current-providing device. Simulation results show scaling factors of 10, 100, 1 k and 10 k. Experimental testing shows the results of the implementation of the floating equivalent multiplier implemented in a notch RLC filter with a scaling factor of 1 k.
This paper formulates the power transfer efficiency of linear passive two-port systems. Focusing on the port voltages and currents, we express the efficiency in terms of impedance matrix components. Algebraic manipulation derives an explicit formula that opens up the vista on how the efficiency behaves on the complex load impedance plane. As a result, we reach a rigorous formula of the maximum efficiency without resorting to reciprocity assumption. This study originates in wireless power transfer engineering, but the hereby deduced formulas are even applicable to performance evaluation of non-reciprocal circuit networks such as ferrite isolators.
A low power hybrid PG_Filter-AGC analog baseband is presented, including a programmable filter (PG_filter) and an auto gain control core (AGC_core). It adopts the digital-plus-analog mixed gain control methodology, resulting in an effective power reduction and a decibel gain error improvement. To further reduce the power of the AGC_core, a low power Variable Gain Amplifier (VGA) adopting sub-threshold design methodology is presented. Furthermore, a self-adaptive threshold voltage compensation (SATC) scheme is proposed to guarantee the good anti-process variation performance for sub-threshold design methodology. The hybrid analog baseband has been fabricated under SMIC 0.18 µm CMOS process, with a die size of 0.45 mm2, where the AGC_core occupies an area of 0.28 mm2. The test results demonstrate a total power of 4.1 mW, where the AGC_core consumes a power of 0.39 mW. A consecutive gain dynamic range of 80 dB, with a decibel gain error small than ±0.39 dB, is achieved and the cutoff frequency ranges from 0.5 MHz∼30 MHz.
A frequency reconfigurable antenna array is presented. The array consists of eight arms with two different feed networks. By controlling PIN diode switches, high frequency array with four dipole elements and low frequency array with two dipole elements can be obtained, respectively. Resonant frequencies within the ranges of 1.0–2.5 GHz (Case I) and 2.5–6.0 GHz (Case II) can be achieved, which translates into an overall tuning ratio of 6:1 (1.0–6.0 GHz) for the antenna array. The proposed antenna array is simulated, fabricated, and tested with good agreement between measurements and simulations.
Based on the negative feedback technique, an ultra-low-power CMOS voltage reference without amplifier is proposed using a 0.18 µm CMOS technology. The proposed voltage reference achieves a temperature coefficient (TC) of 7.2 ppm/°C when the temperature ranges from −20 °C to 80 °C, only consuming 12.8-nA current at room temperature. Besides, the minimum supply voltage is 0.75 V and line sensitivity (LS) is 0.24 mV/V when supply voltage ranges from 0.75 V to 3.5 V. The power supply rejection ratio (PSRR) is only −79 dB at 100 Hz, −56 dB at 1 MHz, respectively.
This paper proposes a method for extending the bandwidth of a three-device Doherty power amplifier (DPA) based on symmetric devices. λ/4 transmission lines are inserted between each peaking amplifier output and carrier amplifier output to compensate load impedance of carrier amplifier. In order to achieve perfect load modulation, carrier amplifier output circuit total electrical length is designed to 90 degrees, and the peak amplifier output total electrical length is designed to 180 degrees. The proposed method is demonstrated by designing a three-device broadband DPA using three 10-W packaged GaN HEMT devices. Measurement results show that over 40% drain efficiency is achieved at 9-dB back-off power, over the frequency band of 1.45–2.35 GHz, accounting for 46% fractional bandwidth.
Among prior short paths padding algorithms, greedy heuristic based on the number of short paths had been proven to be area saving and fast. For ultra-low supply multi-voltage designs, however, delay buffers explode due to improper padding locations caused by unconsidered delay variations. To overcome this problem, we propose a new evaluation function “effectiveness” for greedy heuristic, to characterize the benefit of buffer insertion, thereby to optimize the allocation of padding delay and reduce buffer overhead. An improved algorithm to dynamically update slacks during delay assignment stage is also introduced. Experimental results show average area reduction of 91.6% compared to the prior method.
We numerically investigate the possibility of using Tunnel field-effect transistor (TFET) in a 32 kHz crystal oscillator circuit to reduce power consumption. A simulation using SPICE (Simulation Program with Integrated Circuit Emphasis) is carried out based on a CMOS transistor model. It is shown that the power consumption of TFET is one-tenth that of conventional low-power CMOS.
A 10-bit 1.2 GS/s power efficient time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) is present in this paper. Substrate bias effect depression and output resistance stabilization techniques are provided to enhance the linearity of input buffer. Further, meta-stability restrained trigger comparator is used to enhance the ENOB (effective number of bits) of SAR ADC. Additionally, a digital background calibration technique is proposed to suppress the inter-channel gain, offset and timing skew mismatches. To demonstrate the proposed techniques, a design of time-interleaved SAR ADC is fabricated in 55-nm CMOS technology, consuming 45 mW from 1.2 V power supply with a SNDR of 50 dB and SFDR of 60 dB. The proposed ADC core occupies an active area of 0.84 mm2, and the corresponding FoM is 145 fJ/conversion-step with Nyquist rate.
A major hurdle to adopt 3D stacked DRAM is a thermal problem particularly when the DRAM dies are stacked above the processor dies. Exacerbated thermal problems in DRAM cause another problem which increases refresh rates to ensure data integrity of DRAM cells. In this paper, we propose two efficient techniques to address the thermal problem in 3D die-stacked DRAM by suppressing adverse thermal impacts from the processor die. Our thermal-aware task mapping technique allocates tasks to cores by considering computation-intensiveness of the workloads to minimize thermal interactions. The workload-aware core pipeline control technique adjusts pipeline widths (fetch and issue widths) of processor cores considering the workload characteristics. By adopting our proposed techniques, system-wide energy consumption is reduced by 7.6% while improving performance by 0.4% on average, thanks to the reduced pipeline widths and refresh rates. In terms of temperature, our techniques reduce the number of DRAM banks which exceed 85 degree Celsius by 92.8%, on average.
In recent years, fiber Bragg grating (FBG) strain sensors have been widely applied to measure strain and relative physical quantities. However, the direction of strain must be along the axial or transverse direction of FBG for many FBG sensors, significantly limiting application. Here, the sensing characteristics of FBG for different incident strain waves were determined, and the influences of the incident angle of static strain, low frequency strain, and high frequency strain on FBG sensitivity were characterized. The construction of an FBG strain sensor that can measure strain with any incident angle is proposed, and additional applications of sensing characteristics are discussed.
This paper proposes a sufficient anti-alias and harmonic-reject phase modulation (PM) technique for digital outphasing transmitter. Instead of using complicated spectrum shaping modulation or power-hungry digital-to-analog (DAC) and high-order filters, the proposed less-complex modulation employs cross point estimation (CPE) algorithm to improve the adjacent channel leakage ratio (ACLR) performance and adopts harmonic rejection algorithm to achieve out-of-band (OOB) noise attenuation. When evaluated with a 10 dB peak-to-average power ratio (PAPR) 16 QAM orthogonal-frequency-division-multiplexing (OFDM) signal with a 30 MHz intermediate frequency (IF) carrier, the proposed modulation achieves an ACLR of −65 dBc, providing 17 dB improvement compared with −48 dBc for conventional modulation. Moreover, 56 dB and 57 dB extra attenuations for the 2rd and 3rd images are achieved, respectively.
The equivalent circuit of multi-conductor transmission lines above lossy ground will be more complex compared with one single transmission line above lossy ground, and many problems of matrices need to be solved. In this paper, for multi-conductor transmission lines above lossy ground, the frequency-domain sections of ground impedance matrix and exciting voltage matrix are approximated as the rational function form by the vector fitting (VF) method. So the time domain results can be obtained conveniently by the Laplace element in HSPICE. The DEPACT macro-models and equivalent sources of external electromagnetic fields are built based on voltage controlled current source and voltage controlled voltage source. Then, combined with these equivalent circuits, the equivalent circuits for multi-conductor transmission lines above lossy ground excited by external electromagnetic fields are presented. The simulation results are compared with the finite difference time domain (FDTD) method and good agreement is obtained. Using this approach, the transient responses for multi-conductor transmission lines above lossy ground with nonlinear or frequency-dependent terminations excited by external electromagnetic fields could be obtained quickly and accurately.