2018 Volume 15 Issue 3 Pages 20171235
A 10-bit 1.2 GS/s power efficient time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) is present in this paper. Substrate bias effect depression and output resistance stabilization techniques are provided to enhance the linearity of input buffer. Further, meta-stability restrained trigger comparator is used to enhance the ENOB (effective number of bits) of SAR ADC. Additionally, a digital background calibration technique is proposed to suppress the inter-channel gain, offset and timing skew mismatches. To demonstrate the proposed techniques, a design of time-interleaved SAR ADC is fabricated in 55-nm CMOS technology, consuming 45 mW from 1.2 V power supply with a SNDR of 50 dB and SFDR of 60 dB. The proposed ADC core occupies an active area of 0.84 mm2, and the corresponding FoM is 145 fJ/conversion-step with Nyquist rate.