A low-overhead RO PUF design for Xilinx FPGAs

Abstract

Ring Oscillator (RO) Physical Unclonable Function (PUF) can effectively generate unique chip responses to support a variety of security-related applications. However, RO PUF typically incurs high hardware overhead when implemented in FPGA. In this paper, we designed a low-overhead RO PUF for Xilinx FPGAs, by which, on average, one-bit reliable PUF response can be generated by using only a single CLB (Configurable Logic Block). In the designed RO PUF, two different ROs can be configured in a single CLB at the same time based on the RO construction unit designed in the LUT (Look-Up Table). The designed RO PUF is implemented and verified by Xilinx Spartan 6 FPGA. Experimental results show that the implemented RO PUF has low hardware overhead and satisfactory quality.