A new microstrip balanced-to-balanced diplexer based on stub-loaded dual-mode resonators is presented in this letter. The proposed balanced diplexer primarily consists of two balanced bandpass filter channels, and both channels can be independently designed, thus bringing great flexibility in the diplexer design. Besides, due to the direct connection of two dual-mode balanced filters, no additional matching networks are demanded at the common input port, leading to a significant size reduction. A bandpass coupled line structure is introducing as output feeding line which generates transmission zero on lower side of passband. For demonstration, a prototype balanced diplexer operating at 2.20 and 2.63 GHz is implemented and measured with 3-dB fractional bandwidths of 7.3% and 6.8%. Both simulated and experimental results are provided in satisfactory agreement.

A broadband dual-polarized omnidirectional antenna based on magnetic dipoles is presented. The proposed antenna consists of a cone radiator for vertical polarization (VP) and eight magnetic dipole elements for horizontal polarization (HP). The dipole elements are arranged around the ground plane to greatly reduce the volume of the proposed antenna. The overall volume of the antenna is only π × 75.5 mm × 75.5 mm × 35 mm (about π × 0.25 λ₀ × 0.25 λ₀ × 0.12 λ₀ at 1 GHz). The dipole elements are carefully designed to achieve the bandwidth about 28.7% from 2.03 GHz to 2.71 GHz. The bandwidth of the cone radiator is about 92% covering from 1 GHz to 2.7 GHz with band reject from 1.63 GHz to 1.7 GHz. The port isolation is more than 30 dB at the whole operation band. A good agreement between the simulated and measured results evidently validates this proposed antenna.

A novel pair-wise staggering transmitter is proposed to reduce the crosstalk noise in single-ended channels at high data rates. This work considers two neighboring channels as a pair, and applies staggering between adjacent pairs. As a result, the peak power of crosstalk-induced jitter (CIJ) and glitch (CIG) are reduced by half, so eye becomes larger for a given noise environment, resulting in higher data rate. A prototype IC adopting the proposed approach was fabricated in a 65 nm CMOS process, whose measurement results indicated that the proposed pair-wise 1/2-UI staggering substantially improved the eye height and width at measured operating range of 4.4 to 6.0 Gbps as compared to the conventional 1/2-UI staggering. In terms of maximum data rate, the proposed approach was valid up to over 6 Gbps, whereas the conventional approach was valid merely up to around 4.8 Gbps, indicating 25% improvement.

An ambient illuminance sensor of a mobile device does not always accurately measure the light that directly affects human perception of the display brightness. Thus, viewing high-luminance displays under low-light conditions causes an unbearable glare, while viewing low-luminance displays under bright-light conditions causes very poor visibility. In this paper, an automatic brightness control (ABC) technology depending on pupil area is proposed. The experimental results revealed that the pupil area decreases by 33% as the ambient illuminance increases tenfold. A linear relation was also observed between appropriate display luminance and logarithm of ambient illuminance in our previous investigation. As a result, the comfortable display luminance is proportional to the relative pupil area, which enables us to propose a novel ABC technology depending on the pupil area.

Sorting is an important operation used in various applications including image processing and databases. It represents a large portion of the total execution time of these applications. To improve the performance of sort operations, a dedicated hardware sorter can be used. When implemented in hardware, a FIFO-based merge sorters often shows excellent hardware resource utilization efficiency but requires high buffer memory usage. In this paper, we presents a cost-effective hardware architecture of a FIFO-based merge sorter. Our proposed architecture minimizes buffer memory requirement. We evaluate the design by implementing the architecture on an FPGA platform. FPGA synthesis results show that the proposed approach reduces the average flip-flop and LUT-RAM by 5% and 14%, respectively.

A self-adaptive technique is presented for a low voltage differential signaling (LVDS) driver. By combining a high speed voltage detection circuit and drive capability control loop, the proposed architecture can adapt to the changes of output load and operating frequency automatically. This makes the driver suitable for using in field programmable gate array (FPGA), where load and frequency variation is large. Compared to previously reported LVDS drivers with fixed drive capability, the proposed driver eliminates power wasting under small load and low frequency condition. A prototype chip has been fabricated in 130 nm CMOS technology. Test results show the proposed driver improves maximum bit rate to 2.2 Gb/s and reduces power consumption by 48% compared to previously reported works with fixed drive capability.

This paper presents a 2.4 GHz ISM-band wireless receiver suitable for ultra-low-power (ULP) operation. In this design, a sliding-IF receiver architecture is adopted for achieving desired noise performance with low power consumption. Moreover, a new circuit design method is proposed for achieving ULP design. Some low power circuit techniques such as inverter based amplifier, current reuse and sub-threshold biasing techniques are presented in the design. The proposed receiver is designed and fabricated in a standard 55 nm CMOS process. The measurement results show a voltage gain of 29.2 dB, a noise figure (NF) of 6 dB and third-order intercept point (IIP3) better than −20 dBm. The receiver consumes 2.4 mW from a 1.2-V supply. The core area of the receiver is 0.5 mm².

This paper presents a compact frequency reconfigurable filtering power divider (FRFPD) designed with a single varactor. The proposed FRFPD consists of a “T” type input coupling line, a square loop resonator loaded with a single varactor, and a “π” type output coupling line loaded with a resistor. The tuning frequencies of the proposed FRFPD are analysed in theory. The simulated results demonstrate that the central frequency of the proposed FRFPD can be tuned from 1.85 to 2.10 GHz with insertion loss varied from 1.1 to 3.0 dB. Moreover, the isolation between two output ports is better than 20 dB. The effectiveness of the proposed FRFPD is verified by the measured results.

This paper presents a new anti-harmonic fractional-ratio multiplying delay-locked loop (FMDLL) based clock frequency multiplier for phase aligned on-chip clock generation. With the adoption of a new harmonic lock detector (HLD), the proposed FMDLL solves the harmonic lock problem in conventional MDLLs. The proposed FMDLL is capable of multiplying the input clock with fractional ratio (= N/M), unlike the traditional MDLL which can only multiply with integer ratio (= N). With the new FMDLL, it is possible to quickly change the output frequency or the multiplication factors during operation without a reset. Fabricated in a 65-nm CMOS process, the harmonic-free FMDLL occupies an active area of 0.013 mm², operates from 2 GHz to 4 GHz with programmable ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. At 4 GHz with N/M = 10/1, the measured p-p output clock jitter and RMS jitter are 25.6 ps and 2.62 ps, respectively. The proposed FMDLL consumes 7.16 mW at 4 GHz.

In this letter, a novel one-third mode triangular substrate integrated waveguide resonator (OTMTSIWR) is presented firstly. Compared with the conventional OTMTSIWR, this novel resonator has a lower resonant frequency (f₀) and acceptable unloaded quality (Q_u) to suppress the common-mode (CM) signals, while has more flexibilities to design balanced coupled topology structures. The novel OTMTSIWR and one-sixth mode triangular SIW resonator (OSMTSIWR) can be creatively cascaded together to further reduce filter size. To validate the properties of the novel OTMTSIWR and the above idea, a compact differential bandpass filter (BPF) with a size reduction over 87% is proposed. The filter can produce symmetrical frequency response with one transmission zero (TZ) on each side of the differential-mode (DM) passband by using cross-coupling technology. Meanwhile, good CM suppression is implemented in the DM passband. The measured results are in good agreement with the simulated ones.

A miniaturized dual-band bandpass filter (DBPF) using a pair of composite resonators is proposed in this letter. The composite resonator consists of two vertical short-circuited microstrip lines and a short transversal microstrip line, and its resonant characteristics are analyzed by using the even- and odd-mode method. The even- and odd-mode of the resonator can be controlled individually readily, and hence the DBPF can be designed with a flexible frequency ratio. The DBPF has a compact size of 0.06 λ_g × 0.14 λ_g. To verify the design, a compact DBPF with 3-dB fractional bandwidths of 6% and 7% is designed and fabricated. The measured response is in good agreement with the simulated result.

A new automatic gain control (AGC) scheme in a wideband wireless receiver is presented in this paper. The proposed AGC scheme consists a receiver architecture with tuning the gain of RF amplifier, mixer and IF amplifier synchronously, and a novel exponential function current generator to achieve dB-linear gain control characteristic. Fabricated on a 0.18 um BiCMOS process, the proposed receiver provides a conversion gain dynamic range of 72 dB with the gain ripple of 5 dB that range from 0.8 to 2.7 GHz. At maximum gain operation, the noise figure of 9.9 dB and −25 dBm of third-order input intercept point are measured at 2.7 GHz. The chip draws 27 mW from a 1.8 V power supply and occupies an area of 2.8 mm².

Ring Oscillator (RO) Physical Unclonable Function (PUF) can effectively generate unique chip responses to support a variety of security-related applications. However, RO PUF typically incurs high hardware overhead when implemented in FPGA. In this paper, we designed a low-overhead RO PUF for Xilinx FPGAs, by which, on average, one-bit reliable PUF response can be generated by using only a single CLB (Configurable Logic Block). In the designed RO PUF, two different ROs can be configured in a single CLB at the same time based on the RO construction unit designed in the LUT (Look-Up Table). The designed RO PUF is implemented and verified by Xilinx Spartan 6 FPGA. Experimental results show that the implemented RO PUF has low hardware overhead and satisfactory quality.