IEICE Electronics Express
Online ISSN : 1349-2543
REVIEW PAPER
SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier
Akira MatsuzawaMasaya Miyahara
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JOURNALS FREE ACCESS

2018 Volume 15 Issue 6 Pages 20182002

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Abstract

This paper proposes and discusses SAR+ΔΣADCs with open-loop integrators for low power, high speed, and low noise sensing systems. The integrator uses an open-loop architecture and dynamic amplifier to realize high speed and low power complete integration. Two prototype ADCs have been developed for general purpose and for CMOS image sensors. A high dynamic range of 84 dB and a high Schreier’s FoM of 173 dB have achieved. Furthermore, a high FoM over 170 dB is maintained across a wide range of sampling rate from 2.5 MS/s to 25 MS/s. The SAR+ΔΣADC for CMOS image sensors can reduce the noise down to 66 µV.

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© 2018 by The Institute of Electronics, Information and Communication Engineers
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