As the scaling of LSI is going to extremely fine regions toward the ultimate feature size, one of difficulties faced in analog circuit design is reduction of the dynamic range (DR) due to the supply voltage reduction. Unlike digital circuits, where the noise margin for logic operation is the key criterion, analog circuits need an enough DR. The reduced supply voltage directly results in DR degradation of the conventional analog circuits in the voltage-domain. Especially in mixed-signal LSIs, supply voltage instability, caused by logic operation, tends to degrade DR further. In this paper, we will first discuss potential capability of a new paradigm of time-domain circuits by comparing with the conventional voltage/current-domain circuits in terms of DR and power consumption. Next, as basic circuit components for the time-domain approach, current status of TDA (Time-Difference Amplifier) and TDC (Time-to-Digital Converter) will be reviewed. Finally, some application examples of the time-domain circuits are introduced to demonstrate the feasibility of the time-domain approach.
This paper proposes and discusses SAR+ΔΣADCs with open-loop integrators for low power, high speed, and low noise sensing systems. The integrator uses an open-loop architecture and dynamic amplifier to realize high speed and low power complete integration. Two prototype ADCs have been developed for general purpose and for CMOS image sensors. A high dynamic range of 84 dB and a high Schreier’s FoM of 173 dB have achieved. Furthermore, a high FoM over 170 dB is maintained across a wide range of sampling rate from 2.5 MS/s to 25 MS/s. The SAR+ΔΣADC for CMOS image sensors can reduce the noise down to 66 µV.
In this paper, a permanent magnet synchronous motor controller that improves the robustness to parameter perturbations and load disturbances is proposed for electric drive applications. The speed loop uses global integral sliding mode control strategy, chooses an appropriate global integral sliding surface, maintains a continuous control law, realizes the sliding mode motion throughout the entire motion of the system through a dynamic nonlinear sliding surface, effectively weakens the chattering inherent in the sliding mode control system, and significantly improves the dynamic quality. The load torque sliding mode observer is used to realize the feed-forward compensation of the load torque, the influence on the performance of control system caused by load torque disturbance can be inhibited. The proposed controller is found to be more effective than the conventional controller, as demonstrated through simulations and experiments.
A single-supply level shifter with an internal supply feedback loop, which can shift an input signal from the sub-threshold level to the above-threshold level, is presented in this paper. This level shifter has a wider voltage conversion, less transmission delay, higher energy efficiency, and more flexibility in the physical layout than those described in previous citations. The proposed level shifter can convert a 210-mV input signal into a 1.2-V output signal across process corners with a flexible physical layout when implemented in 65-nm LP technology. For a voltage of 0.2 V, the circuit has a propagation delay of 19.4 ns, a static power dissipation of 1.84 nW, and an energy consumption per transition of 82.2 fJ for a 1-MHz input signal. Due to these excellent characteristics, the proposed design is particularly suitable for applications in multi-voltage digital systems.
In this paper, based on the operation principle and structural features of the Dual Gate Commutated Thyristor (Dual-GCT), a hard-drive simulation circuit model is presented. Dual-GCT is integrated by GCT-A and GCT-B. The Proposed model consists of two Double-M-2T-3R units in parallel which can be used to characterize the Dual-GCT’s switching characteristics and internal commutation mechanism. Then the key model parameters are extracted and the test circuit is established in PSPICE software, and the current and voltage waveform during switching are simulated. The accuracy of the model is verified by comparison of the simulation waveform with the measurement waveform.
In this paper, we analyzed the pulse response from conducting strips with dispersion medium sandwiched air layer by using a combination of fast inversion of Laplace transform (FILT) method and point matching method (PMM), and investigated from pulse response the influence of periodically conducting strips and depth of air layer. From numerical results, we clarified the effect of the air layer, and characteristics of both air layer and periodically conducting strips are showed by differential waveform.
The purpose of this article is to propose a CORDIC-based QR Decomposition (CQRD) for MIMO Signal Detector module with qualities of low-resource and low-latency. The design contains four stages with six CORDIC modules in which its hardware architecture employs both vectoring and rotation mode equations. The evaluated results of CORDIC-based QRD prove that the proposed hardware design is high performance, low resource, and low latency. Because of the advantages of CQRD, it is suitable for the signal detector in MIMO systems.
This letter presents the Cramer–Rao Lower Bound (CRLB) for circularly configured planar arrays. CRLB sets a lower bound on the variance of unbiased estimators. It has been extensively studied in the field of array signal processing especially for direction-of-arrival (DOA) estimation using uniform or non-uniform linear arrays. We consider an underdetermined signal model for circularly configured planar arrays and investigate the conditions under which CRLB exist. A new closed-form expression for the CRLB is derived. We numerically compare the CRLB of uniform circular array (UCA) and nested sparse circular array (NSCA) to confirm whether the proposed formulation is effective for both uniform and non-uniform circular planar arrays.
A Ka band CMOS LO distribution buffer with one single-ended input and three differential outputs is presented. In order to split the input power to three differential ones, a new transformer-based unequal differential three way power divider is proposed and adopted. Based on the traditional dual way power divider transformer, an additional concentric winding loop for the third differential output is implemented in the proposed three-way power divider. Two stages of unit differential cascode amplifier are added to boost the gain and isolation. The area of LO distribution network is only 780 µm × 690 µm and thus is more compact. Measurements show that the output buffer offers a 5.8 dB peak gain at 35.7 GHz with amplitude and phase balances better than 6° and 0.5 dB.