IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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Phase difference analysis technique for parametric faults BIST in CMOS analog circuits
Chatchai WannaboonNattagit JiteurtragoolWimol San-UmMasayoshi Tachibana
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2018 Volume 15 Issue 9 Pages 20180175

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Abstract

Detection of parametric faults is a crucial issue due to the large variation of the fabrication process, which provide a range of acceptable parameter deviations in analog circuits. This paper presents a phase difference analysis technique, which is sensitive to the parametric deviations and allows a tolerance band of passive analog components. Test operations can be simply achieved by comparing the phase difference between a reference clock signal and a reconfigured circuit-under-test (CUT) as an oscillator. The difference of phase characteristics between the two signals can be utilized as an indicator for a fault signature, which can be characterized by a compact digital circuit comprising a counter and logic components. Simulation of faults detection reveals a high faults coverage, high-speed testing, and tolerance band controllability. The proposed technique has offered a fully on-chip BIST in 0.18-µm CMOS standard technology with no external test equipment required.

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© 2018 by The Institute of Electronics, Information and Communication Engineers
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