The performance, power and area optimization with respect to an implementation cost is a fundamental problem in digital circuit design. With a custom design approach, finding patterns of frequent cell combinations can inspire the new cell development and optimization. A FSM (Frequent Subgraph Mining) method can help to develop new cell libraries, however, this requires huge engineering efforts for finding feasible operation conditions. This paper presents an optimized frequent subgraph mining platform by integrating various FSM methods. The experiment results with various designs demonstrate that the proposed method can reduce an overall runtime.

A resistive quenching element is a common passive device used in Geiger mode avalanche photodiode circuits. Both quenching voltage level and response time depend on the resistance value of the quenching resistor. A high resistance value of the quenching resistor increases the transient time due to the large RC time constant. In addition, the quenching voltage level depends on the photocurrent passing through the quenching resistor. In this work, a diode quenching element was proposed by which faster quenching speed was achieved with a constant quenching voltage level independent of the photocurrent level.

Time-interleaved analog to digital convertor (TIADC) is widely used in engineering to increase the sample rate of acquisition system. However, the mismatches between sub-ADCs in TIADC system result in the distortion of sample output and decrease the sample performance. This paper focuses on the calibration of offset, gain and timing skew mismatches. A novel method based on statistical theory is proposed to estimate offset mismatch of each channel. This method can reduce the impact of noise on offset mismatch calibration. The amplitude of main spectrum is utilized to calibrate gain mismatch, and the average value of each sub-ADC is employed to calibrate timing skew mismatch. Meanwhile, gain mismatch and timing skew mismatch are calibrated by STPNM (Simplified Three Point Newton’s method). The proposed calibration method is implemented in a four-channel TIADC based digital storage oscilloscope whose sample rate is 5GSPS. The experiment results show that the impact of mismatches can be reduced effectively and the calibration can be finished in a short time because the convergence is very fast.

Detection of parametric faults is a crucial issue due to the large variation of the fabrication process, which provide a range of acceptable parameter deviations in analog circuits. This paper presents a phase difference analysis technique, which is sensitive to the parametric deviations and allows a tolerance band of passive analog components. Test operations can be simply achieved by comparing the phase difference between a reference clock signal and a reconfigured circuit-under-test (CUT) as an oscillator. The difference of phase characteristics between the two signals can be utilized as an indicator for a fault signature, which can be characterized by a compact digital circuit comprising a counter and logic components. Simulation of faults detection reveals a high faults coverage, high-speed testing, and tolerance band controllability. The proposed technique has offered a fully on-chip BIST in 0.18-µm CMOS standard technology with no external test equipment required.

The high voltage circuit breaker (CB) play an important role in the power systems, so fault diagnosis of CB has great significance. A new fault diagnosis method based on timing parameters and Fuzzy C-means clustering (FCM) is proposed in this paper. First, the cause of CB vibration signal is analyzed theoretically, it is found that the vibration events will be change in different states. Then the short time energy entropy ratio of vibration signal is calculated, which can enhance the impact feature of vibration event. The occurrence time and the end time of vibration events are extracted as feature vector by the double threshold method. Finally, FCM is used to calculate the cluster center of feature vector, depending on the approach degree, fault diagnosis of CB is completed. The experimental test shows that the proposed method can extract feature vector effectively and diagnose the fault type of CB accurately.

This paper presents a Ka band two-stage differential LNA in standard CMOS technology. Neutralized bootstrapped cascode amplifier (NBCA) is implemented to improve the gain and noise performance of the LNA while maintaining the stability. By using 1:3 transformer and larger common gate transistor in the output buffer, the output matching is improved. The effects of neutralization and bootstrapped capacitor on the noise figure, gain and stability are further analyzed. Measurements show that the whole circuit offers a 25 dB peak gain and 4.1 dB NF at 34.5 GHz, with better than 10 dB return losses at the frequency band of interest (33.5 GHz–36 GHz).

Frequency-interleaved ADC (FIADC) is less sensitive of the channel mismatches than the Time-interleaved ADC (TIADC). However, the filter bank mismatches and channel mismatches such as offset, gain and timing mismatches among FIADC still degrade the performance of the FIADC system. This paper presents a new structure of Two-channel Hybrid Filter Banks (HFB) based on power complementary pair, which only need Single-channel filtering. Based on the analysis of channel mismatches and filter bank mismatches, calibration is carried out for FIADC system. Average distortion error of 1.5639 × 10⁻⁵ db and average aliasing error of −93 db can be achieved after calibration by using Third-order analog filter and 64-length digital filters.

In this paper, a noise rejection circuit for level-shift gate drive ICs is proposed. This circuit is composed of a detection module and a pull down module with good process matching robustness and low circuit complexity. The dv/dt noise is removed by monitoring the interval of the IGBT gate-emitter voltage variation and locking the output logic in the period of the dv/dt noise comes. Spectre simulation has been performed with a 700 V 0.6 um BCD process model to verify the performance of the proposed noise rejection circuit which shows a full removal of 80 V/ns dv/dt noise and only 15 ns increasing in propagation delay time.

This letter proposes a filter using a cylindrical quadruple mode SIW resonator. In the proposed resonator, the resonant frequency of each mode can be handled by the number of the ground via in a crisscross arrangement. Also, the external Q-factor of each mode is handled by the length and position of the I/O port line, and thus the filter structure was derived. As a result, it was confirmed that a quadruple-mode filter could be designed.

A compact all-digital duty-cycle and phase-skew correction circuit for quadrature data rate interface-based DRAM applications is presented. To improve the correction time, this work adopts a successive approximation register controller for both duty-cycle and phase-skew correction. The proposed correction circuit has been fabricated in a 65 nm CMOS technology with a die area of 0.086 mm². The duty-cycle and phase-skew of 4-phase outputs are corrected with 56 cycles. The measured duty-cycle error and phase-skew are below ±1% and ±5 ps, respectively.

This paper presents a fully integrated power amplifier (PA) using parallel-combined transistors with a cascode adaptive biasing, implemented in a standard 65 nm CMOS process. The parallel-combined transistors in the common-source stage linearizes the effective g_m. In addition, adaptive bias circuits are applied to both the common-source and common-gate stages to provide optimum operation conditions to each transistor, according to the output power variations. When the fully integrated PA was tested with a modulation and coding scheme 7 (MCS7) 802.11n signal, it meets a −28 dB error vector magnitude and spectral mask requirements at 18.4 dBm of average output power, with a power-added efficiency of 13.1%.