An all-digital duty-cycle and phase-skew correction circuit for QDR DRAMs

Abstract

A compact all-digital duty-cycle and phase-skew correction circuit for quadrature data rate interface-based DRAM applications is presented. To improve the correction time, this work adopts a successive approximation register controller for both duty-cycle and phase-skew correction. The proposed correction circuit has been fabricated in a 65 nm CMOS technology with a die area of 0.086 mm². The duty-cycle and phase-skew of 4-phase outputs are corrected with 56 cycles. The measured duty-cycle error and phase-skew are below ±1% and ±5 ps, respectively.