Near-threshold SIDO DC-DC converter with a high-precision ZCD for phase change memory chip

Jie Miao; Houpeng Chen; Yu Lei; Yi Lv; Weili Liu; Zhitang Song

doi:10.1587/elex.16.20190250

LETTER

Near-threshold SIDO DC-DC converter with a high-precision ZCD for phase change memory chip

Jie Miao, Houpeng Chen, Yu Lei, Yi Lv, Weili Liu, Zhitang Song

Author information

Jie Miao
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences
Houpeng Chen
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences
Yu Lei
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences
Yi Lv
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences
Weili Liu
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences
Zhitang Song
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences

Keywords: DC-DC converter, SIDO, zero current detector

JOURNAL FREE ACCESS

2019 Volume 16 Issue 11 Pages 20190250

DOI https://doi.org/10.1587/elex.16.20190250

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Details

Abstract

This letter proposes a near-threshold single-inductor double-output (SIDO) DC-DC converter with a high-precision zero current detector (ZCD) circuit which supply voltage to phase change memory (PCRAM) chip in wireless sensor network. It has a specific startup procedure to provide wide input voltage range. And the ZCD circuit is designed according to volt-second balance theory and minimizes the duration of reverse inductor current to about 1 nS. The DC-DC converter is implemented in 110 nm standard CMOS process and the maximum power efficiency is 89.47% with no cross regulation.

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