This paper proposes a new method to improve the efficiency of boost converter under light load conditions by using the hybrid modulation of hysteresis current mode and burst mode (HCM-BM). A circuit is designed to satisfy the requirement of adaptive fast switching between HCM and BM. The whole circuit of proposed HCM-BM converter and conventional HCM converter have been built with a standard 0.18-µm CMOS process, respectively. The simulation results show that the proposed converter provides a maximum efficiency improvement of 17% under light load compared with the conventional boost converter. Meantime, it can achieve up to 74% efficiency at 10 µA load.
In this paper, a wideband filtering antenna is designed based on the dual-frequency matching condition. Instead of matching at only one radiating frequency in the conventional filtering antenna design, an antenna element with two radiating frequencies are considered and equivalently modeled as two series-connected parallel RLC resonators, a series inductor, as well as a shunt capacitance. To obtain a wideband impedance matching, last two stages of the parallel coupled-line sections in a filter are synthesized for matching the antenna at two frequencies. Finally, a prototype of a four-pole filtering antenna is designed and fabricated. The measured results achieve a wide bandwidth of 27.8% over 2.12–2.81 GHz with a flat antenna gain of 3.41 dBi over all the filtering band.
In this manuscript, the simplified S-matrix of the pair of RLC circuits with resonant coupling at the resonant frequency is revealed. All of the elements of the S-matrix (S-parameters) are expressed by using essential quantities, which are the port-impedance/resistance ratios and the kQ-product. The matching condition and the maximum power transfer efficiency are analytically derived from the elements of the simplified S-matrix.
We propose a low-overhead, one-cycle timing-error detection and correction (EDAC) technique for flip-flop based pipelines. In order to prevent data collision during local clock gating for rapid error correction, the proposed technique performs clock gating of the master and the slave latches inside the flip-flops independently. Unlike previous flip-flop based one-cycle EDAC techniques, the independent clock gating in the proposed technique enables selective replacement of EDAC flip-flops, thereby reducing the area and power consumption overhead. Our experiments using a 3-stage pipeline consisting of 8-bit multipliers showed that the proposed technique improved the area and power consumption by 66% and 88%, respectively, compared to the state-of-the-art flip-flop based EDAC technique while showing a comparable area and power consumption with the two-phase latch based EDAC technique. A 32-bit, 5-stage MIPS microprocessor data path testchip based on the proposed technique was implemented in a 65 nm CMOS technology. With the proposed one-cycle EDAC technique, the silicon measurement results from 31 dies showed 24.3% higher throughput and 8.7% less energy consumption beyond the point of the first failure (PoFF).
Signal-to-noise ratio (SNR) of the millimeter wave (MMW) three-dimensional (3D) imaging system plays a critical role in the imaging quality. The impacts of phase-locked loop (PLL) bandwidth on SNR of the imaging system is demonstrated and the relationship between SNR and imaging resolution is analyzed in this paper. Analytical and experimental results show that choosing the optimum PLL loop bandwidth can maximize the SNR and greatly improve the performance of MMW imaging system.
Collision Attack (CA) has posed a huge threat to the security of AES circuit. To protect sensitive information, it’s necessary to do research on defense strategy of CA. This letter proposes a new method to defense CA through the implementation of random delay based parallel S-box. It can destroy the consistency of the power consumption curves, confuse the judgment of the collision and the setting of the collision threshold to achieve the goal of resisting the CA. Compared to the well-known random mask method and other CA countermeasures, our strategy can defense CA without changing the AES round transformation architecture and bring extra resource overhead.
This paper proposes a structure of permanent magnet flux-switching motors (PMFSM) using “mixed” segmental permanent magnets, which is based on analysis of the structure and the operational principle of PMFSM. The paper researches the influence of tangential and radial segmental permanent magnets on motor’s electromagnetic torque, torque ripple and cogging torque respectively, which is based on the finite element analysis of a 12/10 three phase permanent magnet flux-switching motor. The research shows that the motors using this new structure can reduce torque ripple and cogging torque by comparing with the conventional permanent magnet flux-switching motor, and the motors have negligible influence on the other performances, such as the flux linkage and the induced voltage.
In this paper, a 14 bit 500 MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40 nm CMOS technology is presented. A 2.5 V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. Besides, the high-voltage-thin-oxide-device design is incorporated to further improve the linearity. In the meantime, an improved supply voltage domain arrangement is proposed to achieve a single power design and improve structural power efficiency. The measured Signal-to-Noise-and-Distortion-Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 71 dB and 79 dBc at 120.2 MHz input signal under 500 MS/s. The ADC occupies an active area of 0.4 mm2 and consumes a total power of 300 mW.
A single event upset (SEU) tolerant latch has been put forward in the current paper. By means of the parallel nodes structure design together with the layout-level optimization design, the proposed design is capable of substantially improving the immunity to SEU. In comparison with the conventional latch, the stacked latch with isolation and the dual-modular-redundancy (DMR) latch with C-element, the simulation results based on the 65 nm CMOS process demonstrate that the proposed latch performs much better in SEU mitigation. For P-hit simulation, the proposed latch can achieve a correct output in the end, no matter the struck PMOS is at OFF state or ON state. For N-hit simulation, the proposed latch is also capable of mitigating the voltage transient and recovering to original state eventually.
In this paper, a 16 times 16 low-power low-area asynchronous iterative multiplier is proposed. The multiplier diminishes 2 bits at a time with an iterative structure, to filter out the useless switching activities, we employ a finishing detector to dynamically detect the end of the computation and stop iteration ahead of schedule. Additionally, with the employment of finishing detectors, the proposed multiplier could provide a much faster average speed than synchronous approach. Post-layout simulation results show that the asynchronous multiplier offers up to 74% power reduction compared with the synchronous design. Simultaneously, the proposed design also exhibits a prominent area reduction compared with other non-iterative multiplier benefited from the iterative architecture.
True time delay lines and phase shifters are widely used in RF timed/phased array systems. Conventional delay lines and phase shifters often associate with reflection type circuits or distributed (periodically loaded) transmission lines. In this paper, we propose a new type of distributed circuit which composed of uniform transmission lines built on integrated Schottky active layer. A bi-functional chip is designed based on the new distributed structure. An Archimedean spiral topology is adopted to reduce the chip area. Theoretical analysis of the design method and circuit parameters is performed and a miniaturized prototype is implemented with p-HEMT technology to validate the design theory. Measurement results shows that this chip could work as either an area-efficient true-time delay line or a low-voltage phase shifter over the bandwidth 11–15 GHz. As an area-efficient true-time delay line, this chip provides 82.1 ps delay time per square millimeter when the biasing voltage fixed at −1.4 V. As a low-voltage phase shifter, this chip provides 26.43° phase shift per volt when the biasing voltage sweeps form 0 V to −1.4 V.
This paper presents a compact varactor-tuned dual-band bandpass filter with independently tunable passbands and high selectivity. The filter consists of two varactor-loaded half-wavelength dual mode resonators, each of which features independent tunability of odd- and even-mode resonant frequencies by varying the capacitances of the corresponding loading varactor diodes. Benefiting from this feature, the filter offers two independently controllable passbands. In addition, hook-shape feed lines are utilized to create transmission zeros between the two passbands, which enhances the selectivity of the filter.
This letter proposes a near-threshold single-inductor double-output (SIDO) DC-DC converter with a high-precision zero current detector (ZCD) circuit which supply voltage to phase change memory (PCRAM) chip in wireless sensor network. It has a specific startup procedure to provide wide input voltage range. And the ZCD circuit is designed according to volt-second balance theory and minimizes the duration of reverse inductor current to about 1 nS. The DC-DC converter is implemented in 110 nm standard CMOS process and the maximum power efficiency is 89.47% with no cross regulation.
In this letter, we present a 30 MHz–3 GHz ultra-broadband GaAs stacked power amplifier (PA) fabricated in 0.15 µm pHEMT process for many applications. The implemented PA obtains 18.9 dB ± 0.9 dB flat gain by using novel input matching networks, and better than 10 dB input and output return loss. The large-signal measurements show that the output power is 30.5 dBm ± 1.2 dB at 12 dBm input power, with a peak PAE of 30% at 400 MHz. For multi-standard system usage, the broadband PA also shows good linearity when tested with two tones and long-term evolution (LTE) signal.
Based on the double folded 1/4 mode substrate integrated waveguide (DFQMSIW) resonator, a two-pole DFQMSIW tunable filter with frequency, bandwidth and transmission zeros tuning is proposed in this paper. In order to increase the stability of the filter, the constant bandwidth can be maintained by changing the coupling coefficient by two varactor diodes when tuning frequency and transmission zeros. The center frequency can be tuned in the range of 1.1 GHz–1.9 GHz, transmission zeros can be tuned from 1.41 GHz to 1.5 GHz with bandwidth unchanged, and bandwidth can be tuned from 120 MHz to 200 MHz. The insertion loss is about −1.3 dB to −3 dB.
This paper presents the resonance transmission of a small, square aperture with two parallel wires in a ground plane. When a plane wave excites a square aperture, aperture resonance occurs using parallel wires, which is known as resonance transmission or maximum power transmission. The resonant frequency of a 3-cm square aperture structure was reduced from 4.18 GHz to various desired frequencies by adding wires. The enhanced transmission cross sections using two parallel wires were ≈3λ2/4π (= 2Gλ2/4π, G = 1.5) for square widths of ≲0.22λ, and approached 3.56λ2/4π (= 2Gλ2/4π, G = 1.78) for square widths ≳0.22λ. The small square aperture enhanced transmission cross sections using parallel wires were between 3λ2/4π and 3.56λ2/4π.
This paper proposes a new two-dimensional (2D) Butler matrix antenna array with 16 switching beams for tile-based beamforming. This study fabricated and assembled a 3.5-GHz Butler switching antenna array using multilayer Rogers printed circuit board technology. It adopted a new design concept and layer-by-layer vertical connection architecture. This 2D Butler matrix antenna array does not require long coaxial cables to connect functional circuit interfaces, which is an improvement over the traditional Butler matrix beamforming network (BFN) antenna array and may facilitate considerable reductions in circuit volume and complexity.
An ultra-wideband (UWB) low-noise amplifier (LNA) exploiting noise cancelling and simultaneous input and noise matching (SINM) technique is presented. The common-gate (CG) input stage with noise cancellation topology is utilized for low-noise figure and wideband input matching. To overcome the noise deterioration induced by the noise-cancelling stages and broaden the input-matching bandwidth, simultaneous input and noise matching technique is employed. The circuit is fabricated in 180-nm CMOS technology. The measurement results show that within 3.1–10.6 GHz UWB applications, S11 is lower than −10 dB, the gain (S21) is 12.4–13.6 dB and the noise figure (NF) is 3.3–4.5 dB. It consumes 12 mA under a 1.8 V supply and occupies an area of 0.56 mm2.